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1. miniSpartan6-plus miniSpartan6-plus Public

   Forked from scarabhardware/miniSpartan6-plus

   Verilog 14 5

2. SpinalHDL SpinalHDL Public

   Forked from SpinalHDL/SpinalHDL

   SpinalHDL core

   Scala

3. caravel_mpw8 caravel_mpw8 Public

   Verilog 2 1

4. SaxonSoc SaxonSoc Public

   Forked from SpinalHDL/SaxonSoc

   SoC based on VexRiscv and ICE40 UP5K

   Scala

5. VexRiscv VexRiscv Public

   Forked from SpinalHDL/VexRiscv

   A FPGA friendly 32 bit RISC-V CPU implementation

   Assembly

6. YosysHQ/apicula YosysHQ/apicula Public

   Project Apicula 🐝: bitstream documentation for Gowin FPGAs

   Verilog 609 83