language: cpp

dist: focal

os: linux

compiler: gcc

services:

- docker

script:

- docker run -ti -v ${PWD}:/work --user $(id -u):$(id -g) -e CCACHE_DIR=/work/.ccache --entrypoint make verilator/verilator:latest

after_success:

- bash <(curl -s https://codecov.io/bash)

ifneq ($(words $(CURDIR)),1)

$(error Unsupported: GNU Make cannot build in directories containing spaces, build elsewhere: '$(CURDIR)')

ifeq ($(VERILATOR_ROOT),)

VERILATOR = verilator

VERILATOR_COVERAGE = verilator_coverage

export VERILATOR_ROOT

VERILATOR = $(VERILATOR_ROOT)/bin/verilator

VERILATOR_COVERAGE = $(VERILATOR_ROOT)/bin/verilator_coverage

VERILATOR_FLAGS =

VERILATOR_FLAGS += -cc --exe

VERILATOR_FLAGS += -Os -x-assign 0

VERILATOR_FLAGS += -Wall

VERILATOR_FLAGS += --assert

VERILATOR_FLAGS += --coverage

VERILATOR_FLAGS += --build -j

VERILATOR_INPUT = -f input.vc top.v sim_main.cpp

VERILATOR_COV_FLAGS += --annotate logs/annotated

VERILATOR_COV_FLAGS += --annotate-min 1

VERILATOR_COV_FLAGS += --write-info logs/coverage.info

VERILATOR_COV_FLAGS += logs/coverage.dat

default: run

run:

@echo

@echo "-- Verilator coverage example"

@echo

@echo "-- VERILATE ----------------"

$(VERILATOR) $(VERILATOR_FLAGS) $(VERILATOR_INPUT)

@echo

@echo "-- RUN ---------------------"

@rm -rf logs

@mkdir -p logs

obj_dir/Vtop

@echo

@echo "-- COVERAGE ----------------"

@rm -rf logs/annotated

$(VERILATOR_COVERAGE) $(VERILATOR_COV_FLAGS)

@echo

@echo "-- DONE --------------------"

show-config:

$(VERILATOR) -V

maintainer-copy::

clean mostlyclean distclean maintainer-clean::

-rm -rf obj_dir logs *.log *.dmp *.vpd core

[](https://travis-ci.org)


[](https://www.codecov.io)


[](https://verilator.org)

[](https://travis-ci.org/verilator/example-systemverilog)

[](https://codecov.io/github/verilator/example-systemverilog?branch=master)

This GitHub is part of [the SystemVerilog Verilator Codecov Tutorial](https://github.com/verilator/example-systemverilog).

The goal of this project is to demonstrate a SystemVerilog project with:

* Verilator

* C++ compiler: `g++`

* Travis-CI running Docker

* Code coverage with `verilator_coverage` (note: it should show the code coverage is below 100%)

* Code coverage published in CodeCov.

We are happy to help if you have any questions. Please contact email our Support at [support@codecov.io](mailto:support@codecov.io)

qmake travis_qmake_gcc_cpp11_gcov.pro

make

// This file typically lists flags required by a large project, e.g. include directories

+libext+.v+.sv+.vh+.svh -y .

#include <verilated.h>

#include "Vtop.h"

vluint64_t main_time = 0;

double sc_time_stamp() {

return main_time; // Note does conversion to real, to match SystemC

}

int main(int argc, char** argv, char** env) {

// This example started with the Verilator example files.

// Please see those examples for commented sources, here:

// https://github.com/verilator/verilator/tree/master/examples

if (0 && argc && argv && env) {}

Verilated::debug(0);

Verilated::randReset(2);

Verilated::traceEverOn(true);

Verilated::commandArgs(argc, argv);

Verilated::mkdir("logs");

Vtop* top = new Vtop; // Or use a const unique_ptr, or the VL_UNIQUE_PTR wrapper

top->clk = 0;

while (!Verilated::gotFinish()) {

++main_time;

top->clk = !top->clk;

top->reset = (main_time < 10) ? 1 : 0;

if (main_time < 5) {

// Zero coverage if still early in reset, otherwise toggles there may

// falsely indicate a signal is covered

VerilatedCov::zero();

}

top->eval();

}

top->final();

// Coverage analysis (since test passed)

#if VM_COVERAGE

Verilated::mkdir("logs");

VerilatedCov::write("logs/coverage.dat");

#endif

delete top;

top = NULL;

exit(0);

}

module top

(input logic clk,

input logic reset);

// Create 100 cycles of example stimulus

reg [31:0] count_c;

always_ff @ (posedge clk) begin

//$display("[%0t] clk=%b reset=%b", $time, clk, reset);

if (reset) begin

count_c <= 0;

end

else begin

count_c <= count_c + 1;

if (count_c >= 99) begin

$write("*-* All Finished *-*\n");

$finish;

end

end

end

// Example coverage analysis

cover property (@(posedge clk) count_c == 30); // Hit

cover property (@(posedge clk) count_c == 300); // Not covered

// Example toggle analysis

wire count_hit_50; // Hit

wire count_hit_500; // Not covered

assign count_hit_50 = (count_c == 50);

assign count_hit_500 = (count_c == 500);

// Example line and block coverage

always_comb begin

if (count_hit_50) begin // Hit

$write("[%0t] got 50\n", $time); // Hit

end

if (count_hit_500) begin // Not covered

$write("[%0t] got 600\n", $time); // Not covered

end

end