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Commit 718aa43

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macdicemacdice
committed
Further tidy-up for old CPU architectures.
Further to commit 92d70b7, let's drop the code we carry for the following untested architectures: M68K, M88K, M32R, SuperH. We have no idea if anything actually works there, and surely as vintage hardware and microcontrollers they would be underpowered for modern purposes. We could always consider re-adding SuperH based on evidence of usage and build farm support, if someone shows up to provide it. While here, SPARC is usually written in all caps. Suggested-by: Tom Lane <tgl@sss.pgh.pa.us> Reviewed-by: Tom Lane <tgl@sss.pgh.pa.us> Reviewed-by: Robert Haas <robertmhaas@gmail.com> (the idea, not the patch) Discussion: https://postgr.es/m/959917.1657522169%40sss.pgh.pa.us
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‎doc/src/sgml/installation.sgml

Copy file name to clipboardExpand all lines: doc/src/sgml/installation.sgml
+2-3Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2125,11 +2125,10 @@ export MANPATH
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<para>
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In general, <productname>PostgreSQL</productname> can be expected to work on
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these CPU architectures: x86, PowerPC, S/390, Sparc, ARM, MIPS, RISC-V,
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these CPU architectures: x86, PowerPC, S/390, SPARC, ARM, MIPS, RISC-V,
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and PA-RISC, including
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big-endian, little-endian, 32-bit, and 64-bit variants where applicable.
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Code support exists for M68K, M88K, M32R, and SuperH, but these
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architectures are not known to have been tested recently. It is often
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It is often
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possible to build on an unsupported CPU type by configuring with
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<option>--disable-spinlocks</option>, but performance will be poor.
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</para>

‎src/backend/storage/lmgr/s_lock.c

Copy file name to clipboardExpand all lines: src/backend/storage/lmgr/s_lock.c
-65Lines changed: 0 additions & 65 deletions
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@@ -220,71 +220,6 @@ update_spins_per_delay(int shared_spins_per_delay)
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}
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/*
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* Various TAS implementations that cannot live in s_lock.h as no inline
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* definition exists (yet).
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* In the future, get rid of tas.[cso] and fold it into this file.
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*
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* If you change something here, you will likely need to modify s_lock.h too,
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* because the definitions for these are split between this file and s_lock.h.
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*/
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#ifdef HAVE_SPINLOCKS /* skip spinlocks if requested */
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#if defined(__GNUC__)
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/*
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* All the gcc flavors that are not inlined
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*/
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/*
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* Note: all the if-tests here probably ought to be testing gcc version
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* rather than platform, but I don't have adequate info to know what to
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* write. Ideally we'd flush all this in favor of the inline version.
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*/
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#if defined(__m68k__) && !defined(__linux__)
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/* really means: extern int tas(slock_t* **lock); */
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static void
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tas_dummy()
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{
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__asm__ __volatile__(
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#if (defined(__NetBSD__) || defined(__OpenBSD__)) && defined(__ELF__)
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/* no underscore for label and % for registers */
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"\
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.global tas \n\
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tas: \n\
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movel %sp@(0x4),%a0 \n\
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tas %a0@ \n\
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beq _success \n\
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moveq #-128,%d0 \n\
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rts \n\
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_success: \n\
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moveq #0,%d0 \n\
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rts \n"
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#else
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"\
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.global _tas \n\
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_tas: \n\
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movel sp@(0x4),a0 \n\
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tas a0@ \n\
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beq _success \n\
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moveq #-128,d0 \n\
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rts \n\
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_success: \n\
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moveq #0,d0 \n\
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rts \n"
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#endif /* (__NetBSD__ || __OpenBSD__) && __ELF__ */
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);
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}
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#endif /* __m68k__ && !__linux__ */
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#endif /* not __GNUC__ */
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#endif /* HAVE_SPINLOCKS */
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/*****************************************************************************/
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#if defined(S_LOCK_TEST)
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‎src/include/storage/s_lock.h

Copy file name to clipboardExpand all lines: src/include/storage/s_lock.h
-102Lines changed: 0 additions & 102 deletions
Original file line numberDiff line numberDiff line change
@@ -498,56 +498,6 @@ do \
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#endif /* powerpc */
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/* Linux Motorola 68k */
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#if (defined(__mc68000__) || defined(__m68k__)) && defined(__linux__)
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#define HAS_TEST_AND_SET
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typedef unsigned char slock_t;
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#define TAS(lock) tas(lock)
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static __inline__ int
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tas(volatile slock_t *lock)
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{
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register int rv;
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__asm__ __volatile__(
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" clrl %0 \n"
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" tas %1 \n"
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" sne %0 \n"
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: "=d"(rv), "+m"(*lock)
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: /* no inputs */
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: "memory", "cc");
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return rv;
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}
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#endif /* (__mc68000__ || __m68k__) && __linux__ */
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/* Motorola 88k */
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#if defined(__m88k__)
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#define HAS_TEST_AND_SET
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typedef unsigned int slock_t;
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#define TAS(lock) tas(lock)
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static __inline__ int
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tas(volatile slock_t *lock)
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{
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register slock_t _res = 1;
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__asm__ __volatile__(
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" xmem %0, %2, %%r0 \n"
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: "+r"(_res), "+m"(*lock)
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: "r"(lock)
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: "memory");
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return (int) _res;
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}
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#endif /* __m88k__ */
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#if defined(__mips__) && !defined(__sgi) /* non-SGI MIPS */
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#define HAS_TEST_AND_SET
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@@ -619,58 +569,6 @@ do \
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#endif /* __mips__ && !__sgi */
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#if defined(__m32r__) && defined(HAVE_SYS_TAS_H) /* Renesas' M32R */
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#define HAS_TEST_AND_SET
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#include <sys/tas.h>
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typedef int slock_t;
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#define TAS(lock) tas(lock)
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#endif /* __m32r__ */
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#if defined(__sh__) /* Renesas' SuperH */
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#define HAS_TEST_AND_SET
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typedef unsigned char slock_t;
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#define TAS(lock) tas(lock)
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static __inline__ int
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tas(volatile slock_t *lock)
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{
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register int _res;
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/*
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* This asm is coded as if %0 could be any register, but actually SuperH
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* restricts the target of xor-immediate to be R0. That's handled by
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* the "z" constraint on _res.
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*/
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__asm__ __volatile__(
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" tas.b @%2 \n"
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" movt %0 \n"
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" xor #1,%0 \n"
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: "=z"(_res), "+m"(*lock)
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: "r"(lock)
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: "memory", "t");
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return _res;
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}
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#endif /* __sh__ */
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/* These live in s_lock.c, but only for gcc */
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#if defined(__m68k__) && !defined(__linux__) /* non-Linux Motorola 68k */
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#define HAS_TEST_AND_SET
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typedef unsigned char slock_t;
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#endif
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#if defined(__hppa) || defined(__hppa__) /* HP PA-RISC */
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/*
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* HP's PA-RISC

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