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Draft: Code generation for arithmetic kernels via pystencils#596

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RichardAngersbach wants to merge 126 commits intoparflow:masterparflow/parflow:masterfrom
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Draft: Code generation for arithmetic kernels via pystencils#596
RichardAngersbach wants to merge 126 commits intoparflow:masterparflow/parflow:masterfrom
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@RichardAngersbach RichardAngersbach commented Mar 26, 2025 •
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This PR integrates code generation via the pystencils Python module into Parflow to provide an alternative solution for achieving performance-portability. This work is conducted in the scope of the EoCoE3 project.

Currently, the following kernels have been replaced:

vector_utilities.c:

  • PFVLinearSum
  • PFVProd
  • PFVDotProd
  • PFVL1Norm

TODOs:

  • Documentation/README
    • Setup guide
    • CMake guide
  • Further replacements for vector utilities or kernels of the non-linear function evaluation
  • Enabling code generation for CUDA/HIP

@RichardAngersbach
Add initial version of coupling with Pystencils
227865b
@RichardAngersbach
Declare generated C++ kernels as extern C and embed in vector_utiliti…
978a62c 
…es.c
@RichardAngersbach
Remove old declaration of KINSpgmrAtimesDQPystencils
0b1876d
@RichardAngersbach
Automatically mark generated function decls as extern C by enabling c…
e5b3e3c 
…_interfacing config
@RichardAngersbach
Add poisson2d testcase for validating pystencils
a98b14a
@RichardAngersbach
Add guards for pystencils coupling
024b5b9
@RichardAngersbach
Fix strides for pystencils vector ops. Set initial reduction variable…
5c8534e 
… for vdotprod and L1 norm to zero
@RichardAngersbach
Use predefined macro for memory alloc needed for reduction
57f39d9
@RichardAngersbach
Move FindPsystencilsSfg and use config module mechanism to facilitate…
f74e6d9 
… porting
@RichardAngersbach
Merge remote-tracking branch 'origin/master'
9df9b22
@RichardAngersbach
Sync with upstream master
a4faf7d
@RichardAngersbach
Refactor name of pystencils generated library and python source for v…
d7d72d7 
…ector util
@RichardAngersbach
Add generated version of PFVScale and refactor abstract pystencils ve…
1c0d1df 
…ctor utility input file
@RichardAngersbach
Correct comment of PFVWrmsNorm
7d01a2c
@RichardAngersbach
Port more vector utility functions to pystencils
70301b3
@RichardAngersbach
Minor indent fix
d31dee0
@RichardAngersbach
Employ pystencils generated vector utility functions in vector_utilit…
cbf2c10 
…ies.c
@RichardAngersbach
Add code generation for PFVCompare
411b9fe
@RichardAngersbach
Prepare CMake and kernel configurations to allow for automatic OpenMP…
b5f6a57 
… parallelization and SIMD vectorization
@RichardAngersbach
Adapt CMake flags fo pystencils support
62c6345
@RichardAngersbach
Fix pystencils SIMD vectorization
3334718
@RichardAngersbach
First steps towards CUDA port
c6883d2
@RichardAngersbach
Progresses on CUDA port: use const pointers for read-only fields
d80f7d5
@RichardAngersbach
Adapt python interpreter selection for pystencils CMake integration
e3952ac
@RichardAngersbach
Minor fixes for SIMD
951cbba
@RichardAngersbach
Omit (now) unnecessary manual marking of const fields - done by pyste…
9285ccc 
…ncils now
@RichardAngersbach
WIP: Try porting kernels from nonlinear eval to pystencils
379cc3f
@RichardAngersbach
Make manually added stride_0 arg for SIMD const
92c0d3f
@RichardAngersbach
Generate kernel adding compressible storage to flux (nonlinear eval)
4b70934
@RichardAngersbach
Generate kernel adding source terms to flux (nonlinear eval)
ef24f41
@RichardAngersbach
Adjust default block sizes for a100 [skip ci]
84b2737
@RichardAngersbach
Add column for number of completed timings to timer [skip ci]
faabf30
@RichardAngersbach
Sync device after launching reduction kernel [skip ci]
d8e8aef
@RichardAngersbach
Add switch for enabling kernel optimizations. Auto-optimize Vdotprod …
3f457b7 
…[skip ci]
@RichardAngersbach
Adapt default block sizes according to block size study [skip ci]
603df5f
@RichardAngersbach
Revert "Adapt default block sizes according to block size study [skip…
102204d 
… ci]"

This reverts commit 603df5f.
@RichardAngersbach
Only do H2D prefetch for reduction wrappers if ptr is init on host be…
a6fe22d 
…fore [skip ci]
@RichardAngersbach
Revert "Reduce number of CPU<->GPU transfers for CUDA reductions"
a30fa70 
This reverts commit 43ee39a.
@RichardAngersbach
Replicate prefetching approach of pf for setting up reduction pointer…
38c2188 
…s in codegen [skip ci]
@RichardAngersbach
Minor adaption of replication for codegen [skip ci]
ee52cc5
@RichardAngersbach
Allow fine-granular timing of vdotprod kernel fo CUDA [skip ci]
02b607f
@RichardAngersbach
Adapt default block sizes according to block size study V2 [skip ci]
edee60d
@RichardAngersbach
Enforce device sync before vdotprod timer [skip ci]
8c6becb
@RichardAngersbach
Increase number of decimals for time logging
0ccf1da
@RichardAngersbach
Add guard for zero element kernel launchs for vdotprod [skip ci]
bb7230b
@RichardAngersbach
Add cub1D-gsl sfg module [skip ci]
7d7ef3e
@RichardAngersbach
Merge remote-tracking branch 'origin/master'
ba8ae2f
@RichardAngersbach
Fix launching of linear1D kernels [skip ci]
0ae85eb
@RichardAngersbach
Adapt block sizes according to new block size study [skip ci]
78b5ea7
@RichardAngersbach
Fix mismatch of max CUDA blocksize and x/y/z components for 3D kernel…
29ac8d0 
…s [skip ci]
@RichardAngersbach
Use SInt(32) as index_dtype for GPUs [skip ci]
6f52e1c
@RichardAngersbach
Adapt block sizes for pure 3d settings again [skip ci]
aab23c0
@RichardAngersbach
Revert "Allow fine-granular timing of vdotprod kernel fo CUDA [skip ci]"
a64c419 
This reverts commit 02b607f
@RichardAngersbach
Get rid of manual launch configurations for GPU codegen
76b6e2b
@RichardAngersbach
Merge remote-tracking branch 'origin/master'
35ff70c
@RichardAngersbach
Merge with ParFlow 3.15 from upstream
7e005d2
@RichardAngersbach
Fix whitespaces
841c430
@RichardAngersbach
Adapt a100 sfg module extensions
c6e6c84
@RichardAngersbach
Fix A100 1D block size to 256
aafcadf
@RichardAngersbach
Adapt CUDA block sizes
693c3ee
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