From 3df90b8f8b133510c4db40bad343d7143281dad9 Mon Sep 17 00:00:00 2001 From: David Green Date: Tue, 13 May 2025 08:45:35 +0100 Subject: [PATCH 1/4] [GlobalISel] Add a GISelValueTracker printing pass This adds a GISelValueTrackingPrinterPass that can print the known bits and sign bit of each def in a function. It is built on the new pass manager and so adds a NPM GISelValueTrackingAnalysis, renaming the older class to GISelValueTrackingAnalysisLegacy. (It could just use GISelValueTracking directly). The first 2 functions from the AArch64GISelMITest are ported over to an mit test to show it working. It also runs successfully on all files in llvm/test/CodeGen/AArch64/GlobalISel/*.mir that are not invalid. --- llvm/docs/GlobalISel/KnownBits.rst | 8 ++-- .../CodeGen/GlobalISel/GISelValueTracking.h | 30 ++++++++++-- llvm/include/llvm/InitializePasses.h | 2 +- .../llvm/Passes/MachinePassRegistry.def | 2 + .../CodeGen/GlobalISel/GISelValueTracking.cpp | 44 +++++++++++++++--- .../CodeGen/GlobalISel/InstructionSelect.cpp | 8 ++-- llvm/lib/CodeGen/GlobalISel/Legalizer.cpp | 9 ++-- llvm/lib/Passes/CMakeLists.txt | 1 + llvm/lib/Passes/PassBuilder.cpp | 1 + .../GISel/AArch64O0PreLegalizerCombiner.cpp | 9 ++-- .../GISel/AArch64PostLegalizerCombiner.cpp | 9 ++-- .../GISel/AArch64PreLegalizerCombiner.cpp | 9 ++-- .../AMDGPU/AMDGPUPostLegalizerCombiner.cpp | 9 ++-- .../AMDGPU/AMDGPUPreLegalizerCombiner.cpp | 9 ++-- .../Target/AMDGPU/AMDGPURegBankCombiner.cpp | 9 ++-- .../Target/Mips/MipsPostLegalizerCombiner.cpp | 9 ++-- .../Target/Mips/MipsPreLegalizerCombiner.cpp | 9 ++-- .../GISel/RISCVO0PreLegalizerCombiner.cpp | 9 ++-- .../GISel/RISCVPostLegalizerCombiner.cpp | 9 ++-- .../RISCV/GISel/RISCVPreLegalizerCombiner.cpp | 9 ++-- llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp | 2 +- .../SPIRV/SPIRVPreLegalizerCombiner.cpp | 9 ++-- .../AArch64/GlobalISel/knownbits-const.mir | 29 ++++++++++++ .../CodeGen/GlobalISel/KnownBitsTest.cpp | 46 ------------------- 24 files changed, 172 insertions(+), 118 deletions(-) create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/knownbits-const.mir diff --git a/llvm/docs/GlobalISel/KnownBits.rst b/llvm/docs/GlobalISel/KnownBits.rst index c01faa5f08f0f..3c61a58626e84 100644 --- a/llvm/docs/GlobalISel/KnownBits.rst +++ b/llvm/docs/GlobalISel/KnownBits.rst @@ -66,7 +66,7 @@ dependency with ``INITIALIZE_PASS_DEPENDENCY``. ... INITIALIZE_PASS_BEGIN(...) - INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysis) + INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy) INITIALIZE_PASS_END(...) and require the pass in ``getAnalysisUsage``. @@ -74,10 +74,10 @@ and require the pass in ``getAnalysisUsage``. .. code-block:: c++ void MyPass::getAnalysisUsage(AnalysisUsage &AU) const { - AU.addRequired(); + AU.addRequired(); // Optional: If your pass preserves known bits analysis (many do) then // indicate that it's preserved for re-use by another pass here. - AU.addPreserved(); + AU.addPreserved(); } Then it's just a matter of fetching the analysis and using it: @@ -86,7 +86,7 @@ Then it's just a matter of fetching the analysis and using it: bool MyPass::runOnMachineFunction(MachineFunction &MF) { ... - GISelValueTracking &VT = getAnalysis().get(MF); + GISelValueTracking &VT = getAnalysis().get(MF); ... MachineInstr *MI = ...; KnownBits Known = VT->getKnownBits(MI->getOperand(0).getReg()); diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GISelValueTracking.h b/llvm/include/llvm/CodeGen/GlobalISel/GISelValueTracking.h index aa99bf321d2b1..d4b4a4e731da7 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/GISelValueTracking.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/GISelValueTracking.h @@ -18,6 +18,7 @@ #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/Register.h" +#include "llvm/IR/PassManager.h" #include "llvm/InitializePasses.h" #include "llvm/Support/KnownBits.h" @@ -104,19 +105,42 @@ class GISelValueTracking : public GISelChangeObserver { /// Eventually add other features such as caching/ser/deserializing /// to MIR etc. Those implementations can derive from GISelValueTracking /// and override computeKnownBitsImpl. -class GISelValueTrackingAnalysis : public MachineFunctionPass { +class GISelValueTrackingAnalysisLegacy : public MachineFunctionPass { std::unique_ptr Info; public: static char ID; - GISelValueTrackingAnalysis() : MachineFunctionPass(ID) { - initializeGISelValueTrackingAnalysisPass(*PassRegistry::getPassRegistry()); + GISelValueTrackingAnalysisLegacy() : MachineFunctionPass(ID) { + initializeGISelValueTrackingAnalysisLegacyPass( + *PassRegistry::getPassRegistry()); } GISelValueTracking &get(MachineFunction &MF); void getAnalysisUsage(AnalysisUsage &AU) const override; bool runOnMachineFunction(MachineFunction &MF) override; void releaseMemory() override { Info.reset(); } }; + +class GISelValueTrackingAnalysis + : public AnalysisInfoMixin { + friend AnalysisInfoMixin; + static AnalysisKey Key; + +public: + using Result = GISelValueTracking; + + Result run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM); +}; + +class GISelValueTrackingPrinterPass + : public PassInfoMixin { + raw_ostream &OS; + +public: + GISelValueTrackingPrinterPass(raw_ostream &OS) : OS(OS) {} + + PreservedAnalyses run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM); +}; } // namespace llvm #endif // LLVM_CODEGEN_GLOBALISEL_GISELVALUETRACKING_H diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h index 0e58caf6478a4..42610d505c2bd 100644 --- a/llvm/include/llvm/InitializePasses.h +++ b/llvm/include/llvm/InitializePasses.h @@ -155,7 +155,7 @@ void initializeLazyValueInfoWrapperPassPass(PassRegistry &); void initializeLegacyLICMPassPass(PassRegistry &); void initializeLegalizerPass(PassRegistry &); void initializeGISelCSEAnalysisWrapperPassPass(PassRegistry &); -void initializeGISelValueTrackingAnalysisPass(PassRegistry &); +void initializeGISelValueTrackingAnalysisLegacyPass(PassRegistry &); void initializeLiveDebugValuesLegacyPass(PassRegistry &); void initializeLiveDebugVariablesWrapperLegacyPass(PassRegistry &); void initializeLiveIntervalsWrapperPassPass(PassRegistry &); diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def index c69573ee3ed97..518dc55acb99b 100644 --- a/llvm/include/llvm/Passes/MachinePassRegistry.def +++ b/llvm/include/llvm/Passes/MachinePassRegistry.def @@ -98,6 +98,7 @@ LOOP_PASS("loop-term-fold", LoopTermFoldPass()) // computed. (We still either need to regenerate kill flags after regalloc, or // preferably fix the scavenger to not depend on them). MACHINE_FUNCTION_ANALYSIS("edge-bundles", EdgeBundlesAnalysis()) +MACHINE_FUNCTION_ANALYSIS("gisel-value-tracking", GISelValueTrackingAnalysis()) MACHINE_FUNCTION_ANALYSIS("livedebugvars", LiveDebugVariablesAnalysis()) MACHINE_FUNCTION_ANALYSIS("live-intervals", LiveIntervalsAnalysis()) MACHINE_FUNCTION_ANALYSIS("live-reg-matrix", LiveRegMatrixAnalysis()) @@ -165,6 +166,7 @@ MACHINE_FUNCTION_PASS("post-RA-sched", PostRASchedulerPass(TM)) MACHINE_FUNCTION_PASS("postmisched", PostMachineSchedulerPass(TM)) MACHINE_FUNCTION_PASS("post-ra-pseudos", ExpandPostRAPseudosPass()) MACHINE_FUNCTION_PASS("print", PrintMIRPass()) +MACHINE_FUNCTION_PASS("print", GISelValueTrackingPrinterPass(errs())) MACHINE_FUNCTION_PASS("print", LiveDebugVariablesPrinterPass(errs())) MACHINE_FUNCTION_PASS("print", LiveIntervalsPrinterPass(errs())) MACHINE_FUNCTION_PASS("print", LiveStacksPrinterPass(errs())) diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp index 89c3801dc203e..028e8d8b46fa9 100644 --- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp +++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp @@ -27,9 +27,9 @@ using namespace llvm; -char llvm::GISelValueTrackingAnalysis::ID = 0; +char llvm::GISelValueTrackingAnalysisLegacy::ID = 0; -INITIALIZE_PASS(GISelValueTrackingAnalysis, DEBUG_TYPE, +INITIALIZE_PASS(GISelValueTrackingAnalysisLegacy, DEBUG_TYPE, "Analysis for ComputingKnownBits", false, true) GISelValueTracking::GISelValueTracking(MachineFunction &MF, unsigned MaxDepth) @@ -485,7 +485,7 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known, else { SrcBitWidth = SrcTy.isPointer() ? DL.getIndexSizeInBits(SrcTy.getAddressSpace()) - : SrcTy.getSizeInBits(); + : SrcTy.getScalarSizeInBits(); } assert(SrcBitWidth && "SrcBitWidth can't be zero"); Known = Known.zextOrTrunc(SrcBitWidth); @@ -889,20 +889,22 @@ unsigned GISelValueTracking::computeNumSignBits(Register R, unsigned GISelValueTracking::computeNumSignBits(Register R, unsigned Depth) { LLT Ty = MRI.getType(R); APInt DemandedElts = - Ty.isVector() ? APInt::getAllOnes(Ty.getNumElements()) : APInt(1, 1); + Ty.isFixedVector() ? APInt::getAllOnes(Ty.getNumElements()) : APInt(1, 1); return computeNumSignBits(R, DemandedElts, Depth); } -void GISelValueTrackingAnalysis::getAnalysisUsage(AnalysisUsage &AU) const { +void GISelValueTrackingAnalysisLegacy::getAnalysisUsage( + AnalysisUsage &AU) const { AU.setPreservesAll(); MachineFunctionPass::getAnalysisUsage(AU); } -bool GISelValueTrackingAnalysis::runOnMachineFunction(MachineFunction &MF) { +bool GISelValueTrackingAnalysisLegacy::runOnMachineFunction( + MachineFunction &MF) { return false; } -GISelValueTracking &GISelValueTrackingAnalysis::get(MachineFunction &MF) { +GISelValueTracking &GISelValueTrackingAnalysisLegacy::get(MachineFunction &MF) { if (!Info) { unsigned MaxDepth = MF.getTarget().getOptLevel() == CodeGenOptLevel::None ? 2 : 6; @@ -910,3 +912,31 @@ GISelValueTracking &GISelValueTrackingAnalysis::get(MachineFunction &MF) { } return *Info; } + +AnalysisKey GISelValueTrackingAnalysis::Key; + +GISelValueTracking +GISelValueTrackingAnalysis::run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM) { + return Result(MF); +} + +PreservedAnalyses +GISelValueTrackingPrinterPass::run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM) { + auto &VTA = MFAM.getResult(MF); + OS << "name: " << MF.getName() << "\n"; + for (MachineBasicBlock &BB : MF) { + for (MachineInstr &MI : BB) { + for (MachineOperand &MO : MI.defs()) { + if (!MO.isReg() || MO.getReg().isPhysical()) + continue; + KnownBits Known = VTA.getKnownBits(MO.getReg()); + unsigned SignedBits = VTA.computeNumSignBits(MO.getReg()); + OS << "KnownBits:" << Known << " SignBits:" << SignedBits << " for " + << MO << "\n"; + }; + } + } + return PreservedAnalyses::all(); +} diff --git a/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp b/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp index 5842f204febf2..194cbc5b2ac87 100644 --- a/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp +++ b/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp @@ -56,7 +56,7 @@ INITIALIZE_PASS_BEGIN(InstructionSelect, DEBUG_TYPE, "Select target instructions out of generic instructions", false, false) INITIALIZE_PASS_DEPENDENCY(TargetPassConfig) -INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysis) +INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy) INITIALIZE_PASS_DEPENDENCY(ProfileSummaryInfoWrapperPass) INITIALIZE_PASS_DEPENDENCY(LazyBlockFrequencyInfoPass) INITIALIZE_PASS_END(InstructionSelect, DEBUG_TYPE, @@ -120,8 +120,8 @@ class InstructionSelect::MIIteratorMaintainer : public GISelChangeObserver { void InstructionSelect::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); if (OptLevel != CodeGenOptLevel::None) { AU.addRequired(); @@ -146,7 +146,7 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) { OptLevel = MF.getFunction().hasOptNone() ? CodeGenOptLevel::None : MF.getTarget().getOptLevel(); - VT = &getAnalysis().get(MF); + VT = &getAnalysis().get(MF); if (OptLevel != CodeGenOptLevel::None) { PSI = &getAnalysis().getPSI(); if (PSI && PSI->hasProfileSummary()) diff --git a/llvm/lib/CodeGen/GlobalISel/Legalizer.cpp b/llvm/lib/CodeGen/GlobalISel/Legalizer.cpp index e4bce16f230b8..1bb3f4bcc9b1b 100644 --- a/llvm/lib/CodeGen/GlobalISel/Legalizer.cpp +++ b/llvm/lib/CodeGen/GlobalISel/Legalizer.cpp @@ -75,7 +75,7 @@ INITIALIZE_PASS_BEGIN(Legalizer, DEBUG_TYPE, false) INITIALIZE_PASS_DEPENDENCY(TargetPassConfig) INITIALIZE_PASS_DEPENDENCY(GISelCSEAnalysisWrapperPass) -INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysis) +INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy) INITIALIZE_PASS_END(Legalizer, DEBUG_TYPE, "Legalize the Machine IR a function's Machine IR", false, false) @@ -86,8 +86,8 @@ void Legalizer::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); AU.addRequired(); AU.addPreserved(); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); getSelectionDAGFallbackAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU); } @@ -341,7 +341,8 @@ bool Legalizer::runOnMachineFunction(MachineFunction &MF) { AuxObservers.push_back(&LocObserver); // This allows Known Bits Analysis in the legalizer. - GISelValueTracking *VT = &getAnalysis().get(MF); + GISelValueTracking *VT = + &getAnalysis().get(MF); const LegalizerInfo &LI = *MF.getSubtarget().getLegalizerInfo(); MFResult Result = legalizeMachineFunction(MF, LI, AuxObservers, LocObserver, diff --git a/llvm/lib/Passes/CMakeLists.txt b/llvm/lib/Passes/CMakeLists.txt index 6425f4934b210..91c8c4f67074d 100644 --- a/llvm/lib/Passes/CMakeLists.txt +++ b/llvm/lib/Passes/CMakeLists.txt @@ -19,6 +19,7 @@ add_llvm_component_library(LLVMPasses Analysis CFGuard CodeGen + GlobalISel Core Coroutines HipStdPar diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp index 7740f622ede7c..8e69683c1d4ce 100644 --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -99,6 +99,7 @@ #include "llvm/CodeGen/FinalizeISel.h" #include "llvm/CodeGen/FixupStatepointCallerSaved.h" #include "llvm/CodeGen/GCMetadata.h" +#include "llvm/CodeGen/GlobalISel/GISelValueTracking.h" #include "llvm/CodeGen/GlobalMerge.h" #include "llvm/CodeGen/GlobalMergeFunctions.h" #include "llvm/CodeGen/HardwareLoops.h" diff --git a/llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp index 460902c67fe35..cca0adc84f6f6 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp @@ -135,8 +135,8 @@ void AArch64O0PreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); AU.setPreservesCFG(); getSelectionDAGFallbackAnalysisUsage(AU); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -153,7 +153,8 @@ bool AArch64O0PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) { auto &TPC = getAnalysis(); const Function &F = MF.getFunction(); - GISelValueTracking *VT = &getAnalysis().get(MF); + GISelValueTracking *VT = + &getAnalysis().get(MF); const AArch64Subtarget &ST = MF.getSubtarget(); @@ -174,7 +175,7 @@ INITIALIZE_PASS_BEGIN(AArch64O0PreLegalizerCombiner, DEBUG_TYPE, "Combine AArch64 machine instrs before legalization", false, false) INITIALIZE_PASS_DEPENDENCY(TargetPassConfig) -INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysis) +INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy) INITIALIZE_PASS_DEPENDENCY(GISelCSEAnalysisWrapperPass) INITIALIZE_PASS_END(AArch64O0PreLegalizerCombiner, DEBUG_TYPE, "Combine AArch64 machine instrs before legalization", false, diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp index 32c33990ad348..1c3d2b4166309 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp @@ -636,8 +636,8 @@ void AArch64PostLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); AU.setPreservesCFG(); getSelectionDAGFallbackAnalysisUsage(AU); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); if (!IsOptNone) { AU.addRequired(); AU.addPreserved(); @@ -668,7 +668,8 @@ bool AArch64PostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) { const AArch64Subtarget &ST = MF.getSubtarget(); const auto *LI = ST.getLegalizerInfo(); - GISelValueTracking *VT = &getAnalysis().get(MF); + GISelValueTracking *VT = + &getAnalysis().get(MF); MachineDominatorTree *MDT = IsOptNone ? nullptr : &getAnalysis().getDomTree(); @@ -883,7 +884,7 @@ INITIALIZE_PASS_BEGIN(AArch64PostLegalizerCombiner, DEBUG_TYPE, "Combine AArch64 MachineInstrs after legalization", false, false) INITIALIZE_PASS_DEPENDENCY(TargetPassConfig) -INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysis) +INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy) INITIALIZE_PASS_END(AArch64PostLegalizerCombiner, DEBUG_TYPE, "Combine AArch64 MachineInstrs after legalization", false, false) diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp index 416386555dc0e..37a7d2206b180 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp @@ -820,8 +820,8 @@ void AArch64PreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); AU.setPreservesCFG(); getSelectionDAGFallbackAnalysisUsage(AU); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); AU.addRequired(); AU.addPreserved(); AU.addRequired(); @@ -852,7 +852,8 @@ bool AArch64PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) { const Function &F = MF.getFunction(); bool EnableOpt = MF.getTarget().getOptLevel() != CodeGenOptLevel::None && !skipFunction(F); - GISelValueTracking *VT = &getAnalysis().get(MF); + GISelValueTracking *VT = + &getAnalysis().get(MF); MachineDominatorTree *MDT = &getAnalysis().getDomTree(); CombinerInfo CInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false, @@ -874,7 +875,7 @@ INITIALIZE_PASS_BEGIN(AArch64PreLegalizerCombiner, DEBUG_TYPE, "Combine AArch64 machine instrs before legalization", false, false) INITIALIZE_PASS_DEPENDENCY(TargetPassConfig) -INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysis) +INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy) INITIALIZE_PASS_DEPENDENCY(GISelCSEAnalysisWrapperPass) INITIALIZE_PASS_END(AArch64PreLegalizerCombiner, DEBUG_TYPE, "Combine AArch64 machine instrs before legalization", false, diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp index a52a6aef2bc39..0c6122cce78e0 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp @@ -462,8 +462,8 @@ void AMDGPUPostLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); AU.setPreservesCFG(); getSelectionDAGFallbackAnalysisUsage(AU); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); if (!IsOptNone) { AU.addRequired(); AU.addPreserved(); @@ -490,7 +490,8 @@ bool AMDGPUPostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) { const AMDGPULegalizerInfo *LI = static_cast(ST.getLegalizerInfo()); - GISelValueTracking *VT = &getAnalysis().get(MF); + GISelValueTracking *VT = + &getAnalysis().get(MF); MachineDominatorTree *MDT = IsOptNone ? nullptr : &getAnalysis().getDomTree(); @@ -512,7 +513,7 @@ INITIALIZE_PASS_BEGIN(AMDGPUPostLegalizerCombiner, DEBUG_TYPE, "Combine AMDGPU machine instrs after legalization", false, false) INITIALIZE_PASS_DEPENDENCY(TargetPassConfig) -INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysis) +INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy) INITIALIZE_PASS_END(AMDGPUPostLegalizerCombiner, DEBUG_TYPE, "Combine AMDGPU machine instrs after legalization", false, false) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp index ca97591a87110..4aec2ba35ae5d 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp @@ -234,8 +234,8 @@ void AMDGPUPreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); AU.setPreservesCFG(); getSelectionDAGFallbackAnalysisUsage(AU); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); if (!IsOptNone) { AU.addRequired(); AU.addPreserved(); @@ -260,7 +260,8 @@ bool AMDGPUPreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) { const Function &F = MF.getFunction(); bool EnableOpt = MF.getTarget().getOptLevel() != CodeGenOptLevel::None && !skipFunction(F); - GISelValueTracking *VT = &getAnalysis().get(MF); + GISelValueTracking *VT = + &getAnalysis().get(MF); // Enable CSE. GISelCSEAnalysisWrapper &Wrapper = @@ -289,7 +290,7 @@ INITIALIZE_PASS_BEGIN(AMDGPUPreLegalizerCombiner, DEBUG_TYPE, "Combine AMDGPU machine instrs before legalization", false, false) INITIALIZE_PASS_DEPENDENCY(TargetPassConfig) -INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysis) +INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy) INITIALIZE_PASS_END(AMDGPUPreLegalizerCombiner, DEBUG_TYPE, "Combine AMDGPU machine instrs before legalization", false, false) diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp index 8f9ad38d101a1..4aee5580b8869 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp @@ -416,8 +416,8 @@ void AMDGPURegBankCombiner::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); AU.setPreservesCFG(); getSelectionDAGFallbackAnalysisUsage(AU); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); if (!IsOptNone) { AU.addRequired(); AU.addPreserved(); @@ -441,7 +441,8 @@ bool AMDGPURegBankCombiner::runOnMachineFunction(MachineFunction &MF) { MF.getTarget().getOptLevel() != CodeGenOptLevel::None && !skipFunction(F); const GCNSubtarget &ST = MF.getSubtarget(); - GISelValueTracking *VT = &getAnalysis().get(MF); + GISelValueTracking *VT = + &getAnalysis().get(MF); const auto *LI = ST.getLegalizerInfo(); MachineDominatorTree *MDT = @@ -466,7 +467,7 @@ INITIALIZE_PASS_BEGIN(AMDGPURegBankCombiner, DEBUG_TYPE, "Combine AMDGPU machine instrs after regbankselect", false, false) INITIALIZE_PASS_DEPENDENCY(TargetPassConfig) -INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysis) +INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy) INITIALIZE_PASS_END(AMDGPURegBankCombiner, DEBUG_TYPE, "Combine AMDGPU machine instrs after regbankselect", false, false) diff --git a/llvm/lib/Target/Mips/MipsPostLegalizerCombiner.cpp b/llvm/lib/Target/Mips/MipsPostLegalizerCombiner.cpp index bb7482c5555ef..166a2501e3f09 100644 --- a/llvm/lib/Target/Mips/MipsPostLegalizerCombiner.cpp +++ b/llvm/lib/Target/Mips/MipsPostLegalizerCombiner.cpp @@ -106,8 +106,8 @@ void MipsPostLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); AU.setPreservesCFG(); getSelectionDAGFallbackAnalysisUsage(AU); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); if (!IsOptNone) { AU.addRequired(); AU.addPreserved(); @@ -134,7 +134,8 @@ bool MipsPostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) { const MipsLegalizerInfo *LI = static_cast(ST.getLegalizerInfo()); - GISelValueTracking *VT = &getAnalysis().get(MF); + GISelValueTracking *VT = + &getAnalysis().get(MF); MachineDominatorTree *MDT = IsOptNone ? nullptr : &getAnalysis().getDomTree(); @@ -150,7 +151,7 @@ INITIALIZE_PASS_BEGIN(MipsPostLegalizerCombiner, DEBUG_TYPE, "Combine Mips machine instrs after legalization", false, false) INITIALIZE_PASS_DEPENDENCY(TargetPassConfig) -INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysis) +INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy) INITIALIZE_PASS_END(MipsPostLegalizerCombiner, DEBUG_TYPE, "Combine Mips machine instrs after legalization", false, false) diff --git a/llvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp b/llvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp index a1ae66ef09770..278dcb143d336 100644 --- a/llvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp +++ b/llvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp @@ -102,8 +102,8 @@ class MipsPreLegalizerCombiner : public MachineFunctionPass { void MipsPreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); AU.setPreservesCFG(); getSelectionDAGFallbackAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU); @@ -122,7 +122,8 @@ bool MipsPreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) { const MipsLegalizerInfo *LI = static_cast(ST.getLegalizerInfo()); - GISelValueTracking *VT = &getAnalysis().get(MF); + GISelValueTracking *VT = + &getAnalysis().get(MF); MipsPreLegalizerCombinerInfo PCInfo; MipsPreLegalizerCombinerImpl Impl(MF, PCInfo, TPC, *VT, /*CSEInfo*/ nullptr, ST, /*MDT*/ nullptr, LI); @@ -134,7 +135,7 @@ INITIALIZE_PASS_BEGIN(MipsPreLegalizerCombiner, DEBUG_TYPE, "Combine Mips machine instrs before legalization", false, false) INITIALIZE_PASS_DEPENDENCY(TargetPassConfig) -INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysis) +INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy) INITIALIZE_PASS_END(MipsPreLegalizerCombiner, DEBUG_TYPE, "Combine Mips machine instrs before legalization", false, false) diff --git a/llvm/lib/Target/RISCV/GISel/RISCVO0PreLegalizerCombiner.cpp b/llvm/lib/Target/RISCV/GISel/RISCVO0PreLegalizerCombiner.cpp index 1450d5f092f9c..d57479c80297d 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVO0PreLegalizerCombiner.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVO0PreLegalizerCombiner.cpp @@ -103,8 +103,8 @@ void RISCVO0PreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); AU.setPreservesCFG(); getSelectionDAGFallbackAnalysisUsage(AU); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -121,7 +121,8 @@ bool RISCVO0PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) { auto &TPC = getAnalysis(); const Function &F = MF.getFunction(); - GISelValueTracking *VT = &getAnalysis().get(MF); + GISelValueTracking *VT = + &getAnalysis().get(MF); const RISCVSubtarget &ST = MF.getSubtarget(); @@ -142,7 +143,7 @@ INITIALIZE_PASS_BEGIN(RISCVO0PreLegalizerCombiner, DEBUG_TYPE, "Combine RISC-V machine instrs before legalization", false, false) INITIALIZE_PASS_DEPENDENCY(TargetPassConfig) -INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysis) +INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy) INITIALIZE_PASS_DEPENDENCY(GISelCSEAnalysisWrapperPass) INITIALIZE_PASS_END(RISCVO0PreLegalizerCombiner, DEBUG_TYPE, "Combine RISC-V machine instrs before legalization", false, diff --git a/llvm/lib/Target/RISCV/GISel/RISCVPostLegalizerCombiner.cpp b/llvm/lib/Target/RISCV/GISel/RISCVPostLegalizerCombiner.cpp index eaccf6d67dcc4..1e4c598d3adf9 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVPostLegalizerCombiner.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVPostLegalizerCombiner.cpp @@ -107,8 +107,8 @@ void RISCVPostLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); AU.setPreservesCFG(); getSelectionDAGFallbackAnalysisUsage(AU); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); AU.addRequired(); AU.addPreserved(); AU.addRequired(); @@ -137,7 +137,8 @@ bool RISCVPostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) { const RISCVSubtarget &ST = MF.getSubtarget(); const auto *LI = ST.getLegalizerInfo(); - GISelValueTracking *VT = &getAnalysis().get(MF); + GISelValueTracking *VT = + &getAnalysis().get(MF); MachineDominatorTree *MDT = &getAnalysis().getDomTree(); GISelCSEAnalysisWrapper &Wrapper = @@ -157,7 +158,7 @@ INITIALIZE_PASS_BEGIN(RISCVPostLegalizerCombiner, DEBUG_TYPE, "Combine RISC-V MachineInstrs after legalization", false, false) INITIALIZE_PASS_DEPENDENCY(TargetPassConfig) -INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysis) +INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy) INITIALIZE_PASS_END(RISCVPostLegalizerCombiner, DEBUG_TYPE, "Combine RISC-V MachineInstrs after legalization", false, false) diff --git a/llvm/lib/Target/RISCV/GISel/RISCVPreLegalizerCombiner.cpp b/llvm/lib/Target/RISCV/GISel/RISCVPreLegalizerCombiner.cpp index afd25676a89eb..e6e8147f3118b 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVPreLegalizerCombiner.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVPreLegalizerCombiner.cpp @@ -105,8 +105,8 @@ void RISCVPreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); AU.setPreservesCFG(); getSelectionDAGFallbackAnalysisUsage(AU); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); AU.addRequired(); AU.addPreserved(); AU.addRequired(); @@ -137,7 +137,8 @@ bool RISCVPreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) { const Function &F = MF.getFunction(); bool EnableOpt = MF.getTarget().getOptLevel() != CodeGenOptLevel::None && !skipFunction(F); - GISelValueTracking *VT = &getAnalysis().get(MF); + GISelValueTracking *VT = + &getAnalysis().get(MF); MachineDominatorTree *MDT = &getAnalysis().getDomTree(); CombinerInfo CInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false, @@ -159,7 +160,7 @@ INITIALIZE_PASS_BEGIN(RISCVPreLegalizerCombiner, DEBUG_TYPE, "Combine RISC-V machine instrs before legalization", false, false) INITIALIZE_PASS_DEPENDENCY(TargetPassConfig) -INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysis) +INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy) INITIALIZE_PASS_DEPENDENCY(GISelCSEAnalysisWrapperPass) INITIALIZE_PASS_END(RISCVPreLegalizerCombiner, DEBUG_TYPE, "Combine RISC-V machine instrs before legalization", false, diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp index 3fcff3dd8f553..b6a2da6e2045d 100644 --- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp @@ -39,7 +39,7 @@ class SPIRVPreLegalizer : public MachineFunctionPass { } // namespace void SPIRVPreLegalizer::getAnalysisUsage(AnalysisUsage &AU) const { - AU.addPreserved(); + AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); } diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizerCombiner.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizerCombiner.cpp index c96ee6b02491a..d378f2b0d1fff 100644 --- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizerCombiner.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizerCombiner.cpp @@ -187,8 +187,8 @@ void SPIRVPreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); AU.setPreservesCFG(); getSelectionDAGFallbackAnalysisUsage(AU); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); AU.addRequired(); AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); @@ -212,7 +212,8 @@ bool SPIRVPreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) { const Function &F = MF.getFunction(); bool EnableOpt = MF.getTarget().getOptLevel() != CodeGenOptLevel::None && !skipFunction(F); - GISelValueTracking *VT = &getAnalysis().get(MF); + GISelValueTracking *VT = + &getAnalysis().get(MF); MachineDominatorTree *MDT = &getAnalysis().getDomTree(); CombinerInfo CInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false, @@ -234,7 +235,7 @@ INITIALIZE_PASS_BEGIN(SPIRVPreLegalizerCombiner, DEBUG_TYPE, "Combine SPIRV machine instrs before legalization", false, false) INITIALIZE_PASS_DEPENDENCY(TargetPassConfig) -INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysis) +INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy) INITIALIZE_PASS_END(SPIRVPreLegalizerCombiner, DEBUG_TYPE, "Combine SPIRV machine instrs before legalization", false, false) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-const.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-const.mir new file mode 100644 index 0000000000000..9199c5ef7448e --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-const.mir @@ -0,0 +1,29 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple aarch64 -passes="print" %s -o - 2>&1 | FileCheck %s + +--- +name: Cst +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: Cst + ; CHECK-NEXT: KnownBits:00000001 SignBits:7 for %0:_ + ; CHECK-NEXT: KnownBits:00000001 SignBits:7 for %1:_ + %0:_(s8) = G_CONSTANT i8 1 + %1:_(s8) = COPY %0 +... +--- +name: CstWithClass +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: CstWithClass + ; We can't analyze %0 due to the register class constraint. We will get a + ; default-constructed KnownBits back. + ; CHECK-NEXT: KnownBits:? SignBits:1 for %0:gpr32 + ; We still don't know the values due to the register class constraint but %1 + ; did reveal the size of %0. + ; CHECK-NEXT: KnownBits:???????????????????????????????? SignBits:1 for %1:_ + %0:gpr32 = MOVi32imm 1 + %1:_(s32) = COPY %0 +... diff --git a/llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp b/llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp index de29cbcd29476..089fb00d6080d 100644 --- a/llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp +++ b/llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp @@ -10,52 +10,6 @@ #include "llvm/CodeGen/GlobalISel/GISelValueTracking.h" #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" -TEST_F(AArch64GISelMITest, TestKnownBitsCst) { - StringRef MIRString = " %3:_(s8) = G_CONSTANT i8 1\n" - " %4:_(s8) = COPY %3\n"; - setUp(MIRString); - if (!TM) - GTEST_SKIP(); - unsigned CopyReg = Copies[Copies.size() - 1]; - MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg); - unsigned SrcReg = FinalCopy->getOperand(1).getReg(); - unsigned DstReg = FinalCopy->getOperand(0).getReg(); - GISelValueTracking Info(*MF); - KnownBits Res = Info.getKnownBits(SrcReg); - EXPECT_EQ((uint64_t)1, Res.One.getZExtValue()); - EXPECT_EQ((uint64_t)0xfe, Res.Zero.getZExtValue()); - - KnownBits Res2 = Info.getKnownBits(DstReg); - EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue()); - EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue()); -} - -TEST_F(AArch64GISelMITest, TestKnownBitsCstWithClass) { - StringRef MIRString = " %10:gpr32 = MOVi32imm 1\n" - " %4:_(s32) = COPY %10\n"; - setUp(MIRString); - if (!TM) - GTEST_SKIP(); - unsigned CopyReg = Copies[Copies.size() - 1]; - MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg); - unsigned SrcReg = FinalCopy->getOperand(1).getReg(); - unsigned DstReg = FinalCopy->getOperand(0).getReg(); - GISelValueTracking Info(*MF); - KnownBits Res = Info.getKnownBits(SrcReg); - // We can't analyze %3 due to the register class constraint. We will get a - // default-constructed KnownBits back. - EXPECT_EQ((uint64_t)1, Res.getBitWidth()); - EXPECT_EQ((uint64_t)0, Res.One.getZExtValue()); - EXPECT_EQ((uint64_t)0, Res.Zero.getZExtValue()); - - KnownBits Res2 = Info.getKnownBits(DstReg); - // We still don't know the values due to the register class constraint but %4 - // did reveal the size of %3. - EXPECT_EQ((uint64_t)32, Res2.getBitWidth()); - EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue()); - EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue()); -} - // Check that we are able to track bits through PHIs // and get the intersections of everything we know on each operand. TEST_F(AArch64GISelMITest, TestKnownBitsCstPHI) { From e09a3708de1e05f504aba22649577263780ca165 Mon Sep 17 00:00:00 2001 From: David Green Date: Tue, 13 May 2025 09:13:35 +0100 Subject: [PATCH 2/4] Remove Scalable vector and vector zext changes --- llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp index 028e8d8b46fa9..bef5495917754 100644 --- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp +++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp @@ -485,7 +485,7 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known, else { SrcBitWidth = SrcTy.isPointer() ? DL.getIndexSizeInBits(SrcTy.getAddressSpace()) - : SrcTy.getScalarSizeInBits(); + : SrcTy.getSizeInBits(); } assert(SrcBitWidth && "SrcBitWidth can't be zero"); Known = Known.zextOrTrunc(SrcBitWidth); @@ -889,7 +889,7 @@ unsigned GISelValueTracking::computeNumSignBits(Register R, unsigned GISelValueTracking::computeNumSignBits(Register R, unsigned Depth) { LLT Ty = MRI.getType(R); APInt DemandedElts = - Ty.isFixedVector() ? APInt::getAllOnes(Ty.getNumElements()) : APInt(1, 1); + Ty.isVector() ? APInt::getAllOnes(Ty.getNumElements()) : APInt(1, 1); return computeNumSignBits(R, DemandedElts, Depth); } From 7882a25d9527b44a6ec8782bcdf47e30e72571fb Mon Sep 17 00:00:00 2001 From: David Green Date: Tue, 13 May 2025 17:27:48 +0100 Subject: [PATCH 3/4] Address comments --- .../lib/CodeGen/GlobalISel/GISelValueTracking.cpp | 15 +++++++++++---- .../AArch64/GlobalISel/knownbits-const.mir | 12 +++++------- 2 files changed, 16 insertions(+), 11 deletions(-) diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp index bef5495917754..27c7a7de3a2a7 100644 --- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp +++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp @@ -925,16 +925,23 @@ PreservedAnalyses GISelValueTrackingPrinterPass::run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM) { auto &VTA = MFAM.getResult(MF); - OS << "name: " << MF.getName() << "\n"; + const auto &MRI = MF.getRegInfo(); + OS << "name: "; + MF.getFunction().printAsOperand(OS, /*PrintType=*/false); + OS << '\n'; + for (MachineBasicBlock &BB : MF) { for (MachineInstr &MI : BB) { for (MachineOperand &MO : MI.defs()) { if (!MO.isReg() || MO.getReg().isPhysical()) continue; - KnownBits Known = VTA.getKnownBits(MO.getReg()); - unsigned SignedBits = VTA.computeNumSignBits(MO.getReg()); + Register Reg = MO.getReg(); + if (!MRI.getType(Reg).isValid()) + continue; + KnownBits Known = VTA.getKnownBits(Reg); + unsigned SignedBits = VTA.computeNumSignBits(Reg); OS << "KnownBits:" << Known << " SignBits:" << SignedBits << " for " - << MO << "\n"; + << MO << '\n'; }; } } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-const.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-const.mir index 9199c5ef7448e..1f33be000858d 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-const.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-const.mir @@ -6,7 +6,7 @@ name: Cst tracksRegLiveness: true body: | bb.1: - ; CHECK-LABEL: name: Cst + ; CHECK-LABEL: name: @Cst ; CHECK-NEXT: KnownBits:00000001 SignBits:7 for %0:_ ; CHECK-NEXT: KnownBits:00000001 SignBits:7 for %1:_ %0:_(s8) = G_CONSTANT i8 1 @@ -14,15 +14,13 @@ body: | ... --- name: CstWithClass +# We can't analyze %0 due to the lack of an LLT. We will get a default +# constructed KnownBits back. %0 will have the correct size but we will +# not know any further info. tracksRegLiveness: true body: | bb.1: - ; CHECK-LABEL: name: CstWithClass - ; We can't analyze %0 due to the register class constraint. We will get a - ; default-constructed KnownBits back. - ; CHECK-NEXT: KnownBits:? SignBits:1 for %0:gpr32 - ; We still don't know the values due to the register class constraint but %1 - ; did reveal the size of %0. + ; CHECK-LABEL: name: @CstWithClass ; CHECK-NEXT: KnownBits:???????????????????????????????? SignBits:1 for %1:_ %0:gpr32 = MOVi32imm 1 %1:_(s32) = COPY %0 From e650de8aafef74e1ec8615570d0c7ccc768a0c1f Mon Sep 17 00:00:00 2001 From: David Green Date: Wed, 14 May 2025 07:59:03 +0100 Subject: [PATCH 4/4] Move the reg to the front --- llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp | 4 ++-- llvm/test/CodeGen/AArch64/GlobalISel/knownbits-const.mir | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp index 27c7a7de3a2a7..589936b6c260f 100644 --- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp +++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp @@ -940,8 +940,8 @@ GISelValueTrackingPrinterPass::run(MachineFunction &MF, continue; KnownBits Known = VTA.getKnownBits(Reg); unsigned SignedBits = VTA.computeNumSignBits(Reg); - OS << "KnownBits:" << Known << " SignBits:" << SignedBits << " for " - << MO << '\n'; + OS << " " << MO << " KnownBits:" << Known << " SignBits:" << SignedBits + << '\n'; }; } } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-const.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-const.mir index 1f33be000858d..5d88bb08ebe72 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-const.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-const.mir @@ -7,8 +7,8 @@ tracksRegLiveness: true body: | bb.1: ; CHECK-LABEL: name: @Cst - ; CHECK-NEXT: KnownBits:00000001 SignBits:7 for %0:_ - ; CHECK-NEXT: KnownBits:00000001 SignBits:7 for %1:_ + ; CHECK-NEXT: %0:_ KnownBits:00000001 SignBits:7 + ; CHECK-NEXT: %1:_ KnownBits:00000001 SignBits:7 %0:_(s8) = G_CONSTANT i8 1 %1:_(s8) = COPY %0 ... @@ -21,7 +21,7 @@ tracksRegLiveness: true body: | bb.1: ; CHECK-LABEL: name: @CstWithClass - ; CHECK-NEXT: KnownBits:???????????????????????????????? SignBits:1 for %1:_ + ; CHECK-NEXT: %1:_ KnownBits:???????????????????????????????? SignBits:1 %0:gpr32 = MOVi32imm 1 %1:_(s32) = COPY %0 ...