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[RISCV][VLOPT] Skip EMUL if it is unknown before entering EMULAndEEWAreEqual #139670

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Merged
merged 4 commits into from
May 14, 2025
Merged

[RISCV][VLOPT] Skip EMUL if it is unknown before entering EMULAndEEWAreEqual #139670

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54ae24e
[RISCV][VLOPT] skip EMUL is unknown before enter EMULAndEEWAreEqual
BeMg May 13, 2025
866f37c
!fixup change on EMULAndEEWAreEqual
BeMg May 14, 2025
ffaabce
!fixup move the testcase
BeMg May 14, 2025
e1a1954
!fixup update format
BeMg May 14, 2025
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5 changes: 5 additions & 0 deletions 5 llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1383,6 +1383,11 @@ RISCVVLOptimizer::checkUsers(const MachineInstr &MI) const {
// If the operand is used as a scalar operand, then the EEW must be
// compatible. Otherwise, the EMUL *and* EEW must be compatible.
bool IsVectorOpUsedAsScalarOp = isVectorOpUsedAsScalarOp(UserOp);

if (!IsVectorOpUsedAsScalarOp &&
(!ConsumerInfo->EMUL || !ProducerInfo->EMUL))
return std::nullopt;

if ((IsVectorOpUsedAsScalarOp &&
!OperandInfo::EEWAreEqual(*ConsumerInfo, *ProducerInfo)) ||
(!IsVectorOpUsedAsScalarOp &&
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22 changes: 22 additions & 0 deletions 22 llvm/test/CodeGen/RISCV/rvv/139288-VLOPT-crash.ll
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Nit, can you move this into vl-opt.ll and replace the VP intrinsics with RISC-V intrinsics? Just in case the VP intrinsics lowering ever changes

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I update the testcase inside the vl-opt.mir.

Original file line number Diff line number Diff line change
@@ -0,0 +1,22 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=riscv64 -mattr=+v < %s | FileCheck %s

define i32 @pps_is_equal(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1) #0 {
; CHECK-LABEL: pps_is_equal:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 1, e32, m8, ta, ma
; CHECK-NEXT: vmclr.m v8
; CHECK-NEXT: vmv.s.x v16, zero
; CHECK-NEXT: vmor.mm v0, v8, v8
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vredmax.vs v8, v8, v16, v0.t
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
entry:
%2 = tail call <vscale x 16 x i1> @llvm.vp.or.nxv16i1(<vscale x 16 x i1> zeroinitializer, <vscale x 16 x i1> zeroinitializer, <vscale x 16 x i1> %0, i32 1)
%3 = tail call i32 @llvm.vp.reduce.smax.nxv16i32(i32 0, <vscale x 16 x i32> zeroinitializer, <vscale x 16 x i1> %2, i32 1)
ret i32 %3
}

declare <vscale x 16 x i1> @llvm.vp.or.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i32) #1
declare i32 @llvm.vp.reduce.smax.nxv16i32(i32, <vscale x 16 x i32>, <vscale x 16 x i1>, i32) #1
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