[AArch64] Extend usage of XAR instruction for fixed-length operations
#139460
Conversation
|
@llvm/pr-subscribers-backend-aarch64 Author: Rajveer Singh Bharadwaj (Rajveer100) ChangesResolves #139229 In #137162, support for Full diff: https://github.com/llvm/llvm-project/pull/139460.diff 1 Files Affected:
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 96fa85179d023..bb059928e33a3 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -4632,18 +4632,38 @@ bool AArch64DAGToDAGISel::trySelectXAR(SDNode *N) {
SDValue Imm = CurDAG->getTargetConstant(
ShAmt, DL, N0.getOperand(1).getValueType(), false);
- if (ShAmt + HsAmt != 64)
+ if (ShAmt + HsAmt != VT.getScalarSizeInBits())
return false;
+ bool UseSVE2Instr = false;
if (!IsXOROperand) {
+ if (VT.getVectorElementType() != MVT::i64 && Subtarget->hasSVE2())
+ UseSVE2Instr = true;
+
SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i64);
SDNode *MOV = CurDAG->getMachineNode(AArch64::MOVIv2d_ns, DL, VT, Zero);
SDValue MOVIV = SDValue(MOV, 0);
+
R1 = N1->getOperand(0);
- R2 = MOVIV;
+ if (UseSVE2Instr) {
+ SDValue ZSub = CurDAG->getTargetConstant(AArch64::zsub, DL, MVT::i32);
+ SDNode *SubRegToReg = CurDAG->getMachineNode(AArch64::SUBREG_TO_REG, DL,
+ VT, Zero, MOVIV, ZSub);
+ R2 = SDValue(SubRegToReg, 0);
+ } else {
+ R2 = MOVIV;
+ }
}
SDValue Ops[] = {R1, R2, Imm};
+ if (UseSVE2Instr) {
+ if (auto Opc = SelectOpcodeFromVT<SelectTypeKind::Int>(
+ VT, {AArch64::XAR_ZZZI_B, AArch64::XAR_ZZZI_H, AArch64::XAR_ZZZI_S,
+ AArch64::XAR_ZZZI_D})) {
+ CurDAG->SelectNodeTo(N, Opc, VT, Ops);
+ return true;
+ }
+ }
CurDAG->SelectNodeTo(N, AArch64::XAR, N0.getValueType(), Ops);
return true;
|
|
@davemgreen |
There was a problem hiding this comment.
I think it will need a INSERT_SUBREG IMPLICIT_DEF, A, zsub for the input and a EXTRACT_SUBREG xar, zsub to make sure the result is kept as the right type for the result.
It can apply to both the rotr(xor(a, b))->xar(a,b) and the rotr(a)->xar(a,0) versions (so it might be easier to expand R1 and R2.
|
I have pushed changes, let me know if this was the intended direction. |
|
✅ With the latest revision this PR passed the C/C++ code formatter. |
134c824 to
60a2ff0
Compare
Resolves llvm#139229 In llvm#137162, support for `v2i64` was implemented for vector rotate transformation, although types like `v4i32`, `v8i16` and `v16i8` do not have Neon SHA3, we can use SVE operations if sve2-sha3 is available.
|
@davemgreen |
Resolves #139229
In #137162, support for
v2i64was implemented for vector rotate transformation, although types likev4i32,v8i16andv16i8do not have Neon SHA3, we can use SVE operations if sve2-sha3 is available.