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[PowerPC] catch v2i64 shift left by 1 is add case #138772

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Merged
merged 2 commits into from
May 13, 2025
Merged

[PowerPC] catch v2i64 shift left by 1 is add case #138772

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0955560
catch v2i64 shift by 1
RolandF77 May 6, 2025
62f06a4
address comment
RolandF77 May 12, 2025
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address comment
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@RolandF77
RolandF77 committed May 12, 2025
commit 62f06a4a333d1a2f46d7026a64ca0f4f6bf902da
11 changes: 6 additions & 5 deletions 11 llvm/lib/Target/PowerPC/PPCISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -18458,16 +18458,17 @@ static SDValue stripModuloOnShift(const TargetLowering &TLI, SDNode *N,

SDValue PPCTargetLowering::combineVectorSHL(SDNode *N,
DAGCombinerInfo &DCI) const {
assert(N->getValueType(0).isVector() && "Vector type expected.");
EVT VT = N->getValueType(0);
assert(VT.isVector() && "Vector type expected.");

SDValue N1 = N->getOperand(1);
if (!Subtarget.hasP8Altivec() || N1.getOpcode() != ISD::BUILD_VECTOR ||
!isOperationLegal(ISD::ADD, N->getValueType(0)))
!isOperationLegal(ISD::ADD, VT))
return SDValue();

// For 64-bit there is no splat immediate so we want to catch shift by 1 here
// before the BUILD_VECTOR is replaced by a load.
EVT EltTy = N->getValueType(0).getScalarType();
EVT EltTy = VT.getScalarType();
if (EltTy != MVT::i64)
return SDValue();

Expand All @@ -18484,8 +18485,8 @@ SDValue PPCTargetLowering::combineVectorSHL(SDNode *N,
if (SplatBits != 1)
return SDValue();

return DCI.DAG.getNode(ISD::ADD, SDLoc(N), N->getValueType(0),
N->getOperand(0), N->getOperand(0));
SDValue N0 = N->getOperand(0);
return DCI.DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
}

SDValue PPCTargetLowering::combineSHL(SDNode *N, DAGCombinerInfo &DCI) const {
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