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[SPARC] Use op-then-halve instructions when we have VIS3 #135718

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Merged
merged 15 commits into from
May 23, 2025
Merged

[SPARC] Use op-then-halve instructions when we have VIS3 #135718

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904fd88
[𝘀𝗽𝗿] changes to main this commit is based on
koachan Apr 15, 2025
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[𝘀𝗽𝗿] initial version
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[𝘀𝗽𝗿] changes introduced through rebase
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Use FPImmLeaf
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[𝘀𝗽𝗿] changes introduced through rebase
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Rebase & update
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[𝘀𝗽𝗿] changes introduced through rebase
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Add vector tests
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[𝘀𝗽𝗿] changes introduced through rebase
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Rebase and apply suggestions
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Rework isFPImmLegal
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18 changes: 13 additions & 5 deletions 18 llvm/lib/Target/Sparc/SparcISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3605,15 +3605,23 @@ bool SparcTargetLowering::useLoadStackGuardNode(const Module &M) const {
return true;
}

bool SparcTargetLowering::isFNegFree(EVT VT) const {
if (Subtarget->isVIS3())
return VT == MVT::f32 || VT == MVT::f64;
return false;
}

bool SparcTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
bool ForCodeSize) const {
bool CanLower = false;
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Suggested change
bool CanLower = false;

if (VT != MVT::f32 && VT != MVT::f64)
return false;
if (Imm.isZero())
return Subtarget->isVIS();
if (Imm.isExactlyValue(+0.5) || Imm.isExactlyValue(-0.5))
return Subtarget->isVIS3();
return false;
if (Subtarget->isVIS())
CanLower = CanLower || Imm.isZero();
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Suggested change
if (Subtarget->isVIS())
CanLower = CanLower || Imm.isZero();
if (Subtarget->isVIS() mm.isZero())
return true;

Did this mean to include -0?

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Yes, +0 and -0.

if (Subtarget->isVIS3())
CanLower =
CanLower || (Imm.isExactlyValue(+0.5) || Imm.isExactlyValue(-0.5));
return CanLower;
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Suggested change
if (Subtarget->isVIS3())
CanLower =
CanLower || (Imm.isExactlyValue(+0.5) || Imm.isExactlyValue(-0.5));
return CanLower;
if (Subtarget->isVIS3())
return Imm.isExactlyValue(+0.5) || Imm.isExactlyValue(-0.5);
return false;

Could also use getExactLog2Abs == -1?

}

bool SparcTargetLowering::isCtlzFast() const { return Subtarget->isVIS3(); }
Expand Down
2 changes: 2 additions & 0 deletions 2 llvm/lib/Target/Sparc/SparcISelLowering.h
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Original file line number Diff line number Diff line change
Expand Up @@ -207,6 +207,8 @@ namespace llvm {
return VT != MVT::f128;
}

bool isFNegFree(EVT VT) const override;

bool isFPImmLegal(const APFloat &Imm, EVT VT,
bool ForCodeSize) const override;

Expand Down
7 changes: 1 addition & 6 deletions 7 llvm/lib/Target/Sparc/SparcInstrVIS.td
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Expand Up @@ -335,17 +335,12 @@ def : Pat<(i64 (bitconvert f64:$src)), (MOVDTOX $src)>;
def : Pat<(f64 (bitconvert i64:$src)), (MOVXTOD $src)>;

// OP-then-neg FP operations.
// TODO handle equivalent patterns like `rs1*-rs2`.
def : Pat<(f32 (fneg (fadd f32:$rs1, f32:$rs2))), (FNADDS $rs1, $rs2)>;
def : Pat<(f64 (fneg (fadd f64:$rs1, f64:$rs2))), (FNADDD $rs1, $rs2)>;
def : Pat<(f32 (fneg (fmul f32:$rs1, f32:$rs2))), (FNMULS $rs1, $rs2)>;
def : Pat<(f32 (fmul (fneg f32:$rs1), f32:$rs2)), (FNMULS $rs1, $rs2)>;
def : Pat<(f32 (fmul f32:$rs1, (fneg f32:$rs2))), (FNMULS $rs1, $rs2)>;
def : Pat<(f64 (fneg (fmul f64:$rs1, f64:$rs2))), (FNMULD $rs1, $rs2)>;
def : Pat<(f64 (fmul (fneg f64:$rs1), f64:$rs2)), (FNMULD $rs1, $rs2)>;
def : Pat<(f64 (fmul f64:$rs1, (fneg f64:$rs2))), (FNMULD $rs1, $rs2)>;
def : Pat<(f64 (fneg (fmul (fpextend f32:$rs1), (fpextend f32:$rs2)))), (FNSMULD $rs1, $rs2)>;
def : Pat<(f64 (fmul (fneg (fpextend f32:$rs1)), (fpextend f32:$rs2))), (FNSMULD $rs1, $rs2)>;
def : Pat<(f64 (fmul (fpextend f32:$rs1), (fneg (fpextend f32:$rs2)))), (FNSMULD $rs1, $rs2)>;

// Op-then-halve FP operations.
def : Pat<(f32 (fmul (fadd f32:$rs1, f32:$rs2), fpimmhalf)), (FHADDS $rs1, $rs2)>;
Expand Down
248 changes: 12 additions & 236 deletions 248 llvm/test/CodeGen/SPARC/float-vis3.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -23,8 +23,8 @@ entry:
ret double %fneg
}

define float @fnmuls1(float %a, float %b) nounwind {
; CHECK-LABEL: fnmuls1:
define float @fnmuls(float %a, float %b) nounwind {
; CHECK-LABEL: fnmuls:
; CHECK: ! %bb.0: ! %entry
; CHECK-NEXT: retl
; CHECK-NEXT: fnmuls %f1, %f3, %f0
Expand All @@ -34,30 +34,8 @@ entry:
ret float %fneg
}

define float @fnmuls2(float %a, float %b) nounwind {
; CHECK-LABEL: fnmuls2:
; CHECK: ! %bb.0: ! %entry
; CHECK-NEXT: retl
; CHECK-NEXT: fnmuls %f1, %f3, %f0
entry:
%fneg = fneg float %a
%mul = fmul float %fneg, %b
ret float %mul
}

define float @fnmuls3(float %a, float %b) nounwind {
; CHECK-LABEL: fnmuls3:
; CHECK: ! %bb.0: ! %entry
; CHECK-NEXT: retl
; CHECK-NEXT: fnmuls %f3, %f1, %f0
entry:
%fneg = fneg float %b
%mul = fmul float %fneg, %a
ret float %mul
}

define double @fnmuld1(double %a, double %b) nounwind {
; CHECK-LABEL: fnmuld1:
define double @fnmuld(double %a, double %b) nounwind {
; CHECK-LABEL: fnmuld:
; CHECK: ! %bb.0: ! %entry
; CHECK-NEXT: retl
; CHECK-NEXT: fnmuld %f0, %f2, %f0
Expand All @@ -67,30 +45,8 @@ entry:
ret double %fneg
}

define double @fnmuld2(double %a, double %b) nounwind {
; CHECK-LABEL: fnmuld2:
; CHECK: ! %bb.0: ! %entry
; CHECK-NEXT: retl
; CHECK-NEXT: fnmuld %f0, %f2, %f0
entry:
%fneg = fneg double %a
%mul = fmul double %fneg, %b
ret double %mul
}

define double @fnmuld3(double %a, double %b) nounwind {
; CHECK-LABEL: fnmuld3:
; CHECK: ! %bb.0: ! %entry
; CHECK-NEXT: retl
; CHECK-NEXT: fnmuld %f2, %f0, %f0
entry:
%fneg = fneg double %b
%mul = fmul double %fneg, %a
ret double %mul
}

define double @fnsmuld1(float %a, float %b) nounwind {
; CHECK-LABEL: fnsmuld1:
define double @fnsmuld(float %a, float %b) nounwind {
; CHECK-LABEL: fnsmuld:
; CHECK: ! %bb.0: ! %entry
; CHECK-NEXT: retl
; CHECK-NEXT: fnsmuld %f1, %f3, %f0
Expand All @@ -102,98 +58,6 @@ entry:
ret double %fneg
}

define double @fnsmuld2(float %a, float %b) nounwind {
; CHECK-LABEL: fnsmuld2:
; CHECK: ! %bb.0: ! %entry
; CHECK-NEXT: retl
; CHECK-NEXT: fnsmuld %f1, %f3, %f0
entry:
%da = fpext float %a to double
%db = fpext float %b to double
%fneg = fneg double %da
%mul = fmul double %fneg, %db
ret double %mul
}

define double @fnsmuld3(float %a, float %b) nounwind {
; CHECK-LABEL: fnsmuld3:
; CHECK: ! %bb.0: ! %entry
; CHECK-NEXT: retl
; CHECK-NEXT: fnsmuld %f3, %f1, %f0
entry:
%da = fpext float %a to double
%db = fpext float %b to double
%fneg = fneg double %db
%mul = fmul double %fneg, %da
ret double %mul
}

define float @fhadds(float %a, float %b) nounwind {
; CHECK-LABEL: fhadds:
; CHECK: ! %bb.0: ! %entry
; CHECK-NEXT: retl
; CHECK-NEXT: fhadds %f1, %f3, %f0
entry:
%add = fadd float %a, %b
%div = fmul float %add, 5.000000e-01
ret float %div
}

define double @fhaddd(double %a, double %b) nounwind {
; CHECK-LABEL: fhaddd:
; CHECK: ! %bb.0: ! %entry
; CHECK-NEXT: retl
; CHECK-NEXT: fhaddd %f0, %f2, %f0
entry:
%add = fadd double %a, %b
%div = fmul double %add, 5.000000e-01
ret double %div
}

define float @fhsubs(float %a, float %b) nounwind {
; CHECK-LABEL: fhsubs:
; CHECK: ! %bb.0: ! %entry
; CHECK-NEXT: retl
; CHECK-NEXT: fhsubs %f1, %f3, %f0
entry:
%sub = fsub float %a, %b
%div = fmul float %sub, 5.000000e-01
ret float %div
}

define double @fhsubd(double %a, double %b) nounwind {
; CHECK-LABEL: fhsubd:
; CHECK: ! %bb.0: ! %entry
; CHECK-NEXT: retl
; CHECK-NEXT: fhsubd %f0, %f2, %f0
entry:
%sub = fsub double %a, %b
%div = fmul double %sub, 5.000000e-01
ret double %div
}

define float @fnhadds(float %a, float %b) nounwind {
; CHECK-LABEL: fnhadds:
; CHECK: ! %bb.0: ! %entry
; CHECK-NEXT: retl
; CHECK-NEXT: fnhadds %f1, %f3, %f0
entry:
%add.i = fadd float %a, %b
%fneg = fmul float %add.i, -5.000000e-01
ret float %fneg
}

define double @fnhaddd(double %a, double %b) nounwind {
; CHECK-LABEL: fnhaddd:
; CHECK: ! %bb.0: ! %entry
; CHECK-NEXT: retl
; CHECK-NEXT: fnhaddd %f0, %f2, %f0
entry:
%add.i = fadd double %a, %b
%fneg = fmul double %add.i, -5.000000e-01
ret double %fneg
}

define <4 x float> @vec_fnadds(<4 x float> %a, <4 x float> %b) nounwind {
; CHECK-LABEL: vec_fnadds:
; CHECK: ! %bb.0: ! %entry
Expand Down Expand Up @@ -222,8 +86,8 @@ entry:
ret <4 x double> %fneg
}

define <4 x float> @vec_fnmuls1(<4 x float> %a, <4 x float> %b) nounwind {
; CHECK-LABEL: vec_fnmuls1:
define <4 x float> @vec_fnmuls(<4 x float> %a, <4 x float> %b) nounwind {
; CHECK-LABEL: vec_fnmuls:
; CHECK: ! %bb.0: ! %entry
; CHECK-NEXT: fnmuls %f1, %f9, %f0
; CHECK-NEXT: fnmuls %f3, %f11, %f1
Expand All @@ -236,36 +100,8 @@ entry:
ret <4 x float> %fneg
}

define <4 x float> @vec_fnmuls2(<4 x float> %a, <4 x float> %b) nounwind {
; CHECK-LABEL: vec_fnmuls2:
; CHECK: ! %bb.0: ! %entry
; CHECK-NEXT: fnmuls %f1, %f9, %f0
; CHECK-NEXT: fnmuls %f3, %f11, %f1
; CHECK-NEXT: fnmuls %f5, %f13, %f2
; CHECK-NEXT: retl
; CHECK-NEXT: fnmuls %f7, %f15, %f3
entry:
%fneg = fneg <4 x float> %a
%mul = fmul <4 x float> %fneg, %b
ret <4 x float> %mul
}

define <4 x float> @vec_fnmuls3(<4 x float> %a, <4 x float> %b) nounwind {
; CHECK-LABEL: vec_fnmuls3:
; CHECK: ! %bb.0: ! %entry
; CHECK-NEXT: fnmuls %f9, %f1, %f0
; CHECK-NEXT: fnmuls %f11, %f3, %f1
; CHECK-NEXT: fnmuls %f13, %f5, %f2
; CHECK-NEXT: retl
; CHECK-NEXT: fnmuls %f15, %f7, %f3
entry:
%fneg = fneg <4 x float> %b
%mul = fmul <4 x float> %fneg, %a
ret <4 x float> %mul
}

define <4 x double> @vec_nmuld1(<4 x double> %a, <4 x double> %b) nounwind {
; CHECK-LABEL: vec_nmuld1:
define <4 x double> @vec_fnmuld(<4 x double> %a, <4 x double> %b) nounwind {
; CHECK-LABEL: vec_fnmuld:
; CHECK: ! %bb.0: ! %entry
; CHECK-NEXT: fnmuld %f0, %f8, %f0
; CHECK-NEXT: fnmuld %f2, %f10, %f2
Expand All @@ -278,36 +114,8 @@ entry:
ret <4 x double> %fneg
}

define <4 x double> @vec_fnmuld2(<4 x double> %a, <4 x double> %b) nounwind {
; CHECK-LABEL: vec_fnmuld2:
; CHECK: ! %bb.0: ! %entry
; CHECK-NEXT: fnmuld %f0, %f8, %f0
; CHECK-NEXT: fnmuld %f2, %f10, %f2
; CHECK-NEXT: fnmuld %f4, %f12, %f4
; CHECK-NEXT: retl
; CHECK-NEXT: fnmuld %f6, %f14, %f6
entry:
%fneg = fneg <4 x double> %a
%mul = fmul <4 x double> %fneg, %b
ret <4 x double> %mul
}

define <4 x double> @vec_fnmuld3(<4 x double> %a, <4 x double> %b) nounwind {
; CHECK-LABEL: vec_fnmuld3:
; CHECK: ! %bb.0: ! %entry
; CHECK-NEXT: fnmuld %f8, %f0, %f0
; CHECK-NEXT: fnmuld %f10, %f2, %f2
; CHECK-NEXT: fnmuld %f12, %f4, %f4
; CHECK-NEXT: retl
; CHECK-NEXT: fnmuld %f14, %f6, %f6
entry:
%fneg = fneg <4 x double> %b
%mul = fmul <4 x double> %fneg, %a
ret <4 x double> %mul
}

define <4 x double> @vec_fnsmuld1(<4 x float> %a, <4 x float> %b) nounwind {
; CHECK-LABEL: vec_fnsmuld1:
define <4 x double> @vec_fnsmuld(<4 x float> %a, <4 x float> %b) nounwind {
; CHECK-LABEL: vec_fnsmuld:
; CHECK: ! %bb.0: ! %entry
; CHECK-NEXT: fnsmuld %f1, %f9, %f0
; CHECK-NEXT: fnsmuld %f3, %f11, %f2
Expand All @@ -322,38 +130,6 @@ entry:
ret <4 x double> %fneg
}

define <4 x double> @vec_fnsmuld2(<4 x float> %a, <4 x float> %b) nounwind {
; CHECK-LABEL: vec_fnsmuld2:
; CHECK: ! %bb.0: ! %entry
; CHECK-NEXT: fnsmuld %f1, %f9, %f0
; CHECK-NEXT: fnsmuld %f3, %f11, %f2
; CHECK-NEXT: fnsmuld %f5, %f13, %f4
; CHECK-NEXT: retl
; CHECK-NEXT: fnsmuld %f7, %f15, %f6
entry:
%da = fpext <4 x float> %a to <4 x double>
%db = fpext <4 x float> %b to <4 x double>
%fneg = fneg <4 x double> %da
%mul = fmul <4 x double> %fneg, %db
ret <4 x double> %mul
}

define <4 x double> @vec_fnsmuld3(<4 x float> %a, <4 x float> %b) nounwind {
; CHECK-LABEL: vec_fnsmuld3:
; CHECK: ! %bb.0: ! %entry
; CHECK-NEXT: fnsmuld %f9, %f1, %f0
; CHECK-NEXT: fnsmuld %f11, %f3, %f2
; CHECK-NEXT: fnsmuld %f13, %f5, %f4
; CHECK-NEXT: retl
; CHECK-NEXT: fnsmuld %f15, %f7, %f6
entry:
%da = fpext <4 x float> %a to <4 x double>
%db = fpext <4 x float> %b to <4 x double>
%fneg = fneg <4 x double> %db
%mul = fmul <4 x double> %fneg, %da
ret <4 x double> %mul
}

define <4 x float> @vec_fhadds(<4 x float> %a, <4 x float> %b) nounwind {
; CHECK-LABEL: vec_fhadds:
; CHECK: ! %bb.0: ! %entry
Expand Down
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