Format

llvm · SamTebbs33 · Nov 15, 2024 · Jan 10, 2025 · Jan 15, 2025 · Jan 16, 2025
commit f6718e39b220f5114a886b799cc5564b42a485e2
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -5340,24 +5340,32 @@ SDValue AArch64TargetLowering::LowerALIAS_LANE_MASK(SDValue Op,
  // Make sure that the promoted mask size and element size match
  switch (EltSize) {
  case 1:
+    IntrinsicID = IsWriteAfterRead ? Intrinsic::aarch64_sve_whilewr_b
+                                   : Intrinsic::aarch64_sve_whilerw_b;
    assert((SimpleVT == MVT::v16i8 || SimpleVT == MVT::nxv16i1) &&
           "Unexpected mask or element size");
    IntrinsicID = IsWriteAfterRead ? Intrinsic::aarch64_sve_whilewr_b
                                   : Intrinsic::aarch64_sve_whilerw_b;
    break;
  case 2:
+    IntrinsicID = IsWriteAfterRead ? Intrinsic::aarch64_sve_whilewr_h
+                                   : Intrinsic::aarch64_sve_whilerw_h;
    assert((SimpleVT == MVT::v8i8 || SimpleVT == MVT::nxv8i1) &&
           "Unexpected mask or element size");
    IntrinsicID = IsWriteAfterRead ? Intrinsic::aarch64_sve_whilewr_h
                                   : Intrinsic::aarch64_sve_whilerw_h;
    break;
  case 4:
+    IntrinsicID = IsWriteAfterRead ? Intrinsic::aarch64_sve_whilewr_s
+                                   : Intrinsic::aarch64_sve_whilerw_s;
    assert((SimpleVT == MVT::v4i16 || SimpleVT == MVT::nxv4i1) &&
           "Unexpected mask or element size");
    IntrinsicID = IsWriteAfterRead ? Intrinsic::aarch64_sve_whilewr_s
                                   : Intrinsic::aarch64_sve_whilerw_s;
    break;
  case 8:
+    IntrinsicID = IsWriteAfterRead ? Intrinsic::aarch64_sve_whilewr_d
+                                   : Intrinsic::aarch64_sve_whilerw_d;
    assert((SimpleVT == MVT::v2i32 || SimpleVT == MVT::nxv2i1) &&
           "Unexpected mask or element size");
    IntrinsicID = IsWriteAfterRead ? Intrinsic::aarch64_sve_whilewr_d