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[SelectionDAG] Allow vselect in foldBinOpIntoSelect
backend:X86
llvm:SelectionDAG
SelectionDAGISel as well
#143283
opened Jun 7, 2025 by
AZero13
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[X86][SDAG] Infinite loop at O3
backend:X86
generated by fuzzer
hang
Compiler hang (infinite loop)
llvm:SelectionDAG
SelectionDAGISel as well
#143238
opened Jun 7, 2025 by
dtcxzyw
[SelectionDAG] Deal with POISON for INSERT_VECTOR_ELT/INSERT_SUBVECTOR (part 3)
backend:AArch64
backend:RISC-V
backend:X86
llvm:SelectionDAG
SelectionDAGISel as well
#143105
opened Jun 6, 2025 by
bjope
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[SelectionDAG] Deal with POISON for INSERT_VECTOR_ELT/INSERT_SUBVECTOR (part 2)
backend:AArch64
backend:X86
llvm:SelectionDAG
SelectionDAGISel as well
#143103
opened Jun 6, 2025 by
bjope
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[SelectionDAG] Deal with POISON for INSERT_VECTOR_ELT/INSERT_SUBVECTOR (part 1)
backend:AArch64
backend:AMDGPU
backend:X86
llvm:SelectionDAG
SelectionDAGISel as well
#143102
opened Jun 6, 2025 by
bjope
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DAG: Move soft float predicate management into RuntimeLibcalls
backend:ARM
backend:MSP430
llvm:ir
llvm:SelectionDAG
SelectionDAGISel as well
#142905
opened Jun 5, 2025 by
arsenm
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DAG: Assert fcmp uno runtime calls are boolean values
backend:ARM
backend:X86
llvm:SelectionDAG
SelectionDAGISel as well
#142898
opened Jun 5, 2025 by
arsenm
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[AMDGPU][SDAG] Handle ISD::PTRADD in SelectionDAGAddressAnalysis
backend:AMDGPU
llvm:SelectionDAG
SelectionDAGISel as well
#142778
opened Jun 4, 2025 by
ritter-x2a
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[AMDGPU][SDAG] Add ISD::PTRADD DAG combines
backend:AMDGPU
llvm:SelectionDAG
SelectionDAGISel as well
#142739
opened Jun 4, 2025 by
ritter-x2a
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llvm.canonicalize in common code
backend:AArch64
backend:AMDGPU
backend:loongarch
backend:PowerPC
backend:SystemZ
llvm:codegen
llvm:SelectionDAG
#142105
opened May 30, 2025 by
dominik-steenken
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[AMDGPU][SDAG] Initial support for ISD::PTRADD
backend:AMDGPU
llvm:globalisel
llvm:SelectionDAG
SelectionDAGISel as well
#141725
opened May 28, 2025 by
ritter-x2a
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[DAG] WidenVectorResult - add support for ISD::VECTOR_INTERLEAVE/ISD::VECTOR_DEINTERLEAVE nodes
llvm:SelectionDAG
SelectionDAGISel as well
#141569
opened May 27, 2025 by
RKSimon
[DAG] Fold (and X, (add (not Y), Z)) -> (and X, (not (sub Y, Z))).
backend:AArch64
backend:loongarch
backend:X86
llvm:SelectionDAG
SelectionDAGISel as well
#141476
opened May 26, 2025 by
simonzgx
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[X86] SelectionDAGISel as well
missed-optimization
const << (x&7) doesn't use shlx when BMI2 is available
backend:X86
llvm:SelectionDAG
#141347
opened May 24, 2025 by
dzaima
[SDAG] Add partial_reduce_sumla node
backend:AArch64
backend:RISC-V
llvm:SelectionDAG
SelectionDAGISel as well
#141267
opened May 23, 2025 by
preames
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SelectionDAG::getNode may fold UNDEF to POISON
llvm:SelectionDAG
SelectionDAGISel as well
#141034
opened May 22, 2025 by
bjope
[WebAssembly][Clang] Prefer [crash-on-valid] or [crash-on-invalid]
llvm:SelectionDAG
SelectionDAGISel as well
_externref_t usage in global scope emits fatal error in backend
backend:WebAssembly
crash
#141011
opened May 22, 2025 by
Losy001
[GISel][AArch64] Allow PatLeafs to be imported in GISel which were previously causing warnings
backend:AArch64
llvm:globalisel
llvm:SelectionDAG
SelectionDAGISel as well
tablegen
#140935
opened May 21, 2025 by
jyli0116
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WASM crash when using __funcref
backend:WebAssembly
crash
Prefer [crash-on-valid] or [crash-on-invalid]
llvm:SelectionDAG
SelectionDAGISel as well
#140933
opened May 21, 2025 by
glingy
a & ~(a - b) optimizes to a & (~a + b) even though most targets have an ANDN instruction
good first issue
#140639
opened May 19, 2025 by
Validark
[arm] Cannot select SelectionDAGISel as well
i32 = setcc 0x00000000, Constant:i64
crash-on-valid
llvm:SelectionDAG
#140445
opened May 18, 2025 by
Urgau
[IR] Add llvm SelectionDAGISel as well
clmul intrinsic
backend:RISC-V
llvm:ir
llvm:SelectionDAG
#140301
opened May 16, 2025 by
oscardssmith
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expandFMINIMUMNUM_FMAXIMUMNUM: Improve compare between zeros
backend:AMDGPU
backend:X86
llvm:SelectionDAG
SelectionDAGISel as well
#140193
opened May 16, 2025 by
wzssyqa
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clang crashed when build pdclib for taget bpf
backend:BPF
crash
Prefer [crash-on-valid] or [crash-on-invalid]
llvm:SelectionDAG
SelectionDAGISel as well
#139850
opened May 14, 2025 by
choury
[SwitchLowering] Support merging 0 and power-of-2 case.
backend:AArch64
llvm:globalisel
llvm:SelectionDAG
SelectionDAGISel as well
#139736
opened May 13, 2025 by
fhahn
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