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Commit ba567c1

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[GISel][AArch64] Removed unused function declaration and brackets
1 parent b1040e7 commit ba567c1
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-16
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3 files changed

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‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

Copy file name to clipboardExpand all lines: llvm/lib/Target/AArch64/AArch64InstrInfo.td
+4-4Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -687,7 +687,7 @@ def top16Zero: PatLeaf<(i32 GPR32:$src), [{
687687
CurDAG->MaskedValueIsZero(Op, APInt::getHighBitsSet(32, 16));
688688
}]> {
689689
let GISelLeafPredicateCode = [{
690-
return (VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(32, 16))); }];
690+
return VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(32, 16)); }];
691691
}
692692

693693
// top32Zero - answer true if the upper 32 bits of $src are 0, false otherwise
@@ -696,7 +696,7 @@ def top32Zero: PatLeaf<(i64 GPR64:$src), [{
696696
CurDAG->MaskedValueIsZero(Op, APInt::getHighBitsSet(64, 32));
697697
}]> {
698698
let GISelLeafPredicateCode = [{
699-
return (VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(64, 32))); }];
699+
return VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(64, 32)); }];
700700
}
701701

702702
// topbitsallzero - Return true if all bits except the lowest bit are known zero
@@ -705,14 +705,14 @@ def topbitsallzero32: PatLeaf<(i32 GPR32:$src), [{
705705
CurDAG->MaskedValueIsZero(Op, APInt::getHighBitsSet(32, 31));
706706
}]> {
707707
let GISelLeafPredicateCode = [{
708-
return (VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(32, 31))); }];
708+
return VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(32, 31)); }];
709709
}
710710
def topbitsallzero64: PatLeaf<(i64 GPR64:$src), [{
711711
return Op.getValueType() == MVT::i64 &&
712712
CurDAG->MaskedValueIsZero(Op, APInt::getHighBitsSet(64, 63));
713713
}]> {
714714
let GISelLeafPredicateCode = [{
715-
return (VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(64, 63))); }];
715+
return VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(64, 63)); }];
716716
}
717717

718718
// Node definitions.

‎llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

Copy file name to clipboardExpand all lines: llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
-10Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -511,16 +511,6 @@ class AArch64InstructionSelector : public InstructionSelector {
511511
/// Return true if \p MI is a load or store of \p NumBytes bytes.
512512
bool isLoadStoreOfNumBytes(const MachineInstr &MI, unsigned NumBytes) const;
513513

514-
/// Return true if top 16 bits of register are zero.
515-
bool isTop16Zero(const MachineOperand &MO) const;
516-
517-
/// Return true if top 32 bits of register are zero.
518-
bool isTop32Zero(const MachineOperand &MO) const;
519-
520-
/// Return true if all bits of register except the lowest bit are known zero.
521-
bool isTopBitsAllZero32(const MachineOperand &MO) const;
522-
bool isTopBitsAllZero64(const MachineOperand &MO) const;
523-
524514
/// Returns true if \p MI is guaranteed to have the high-half of a 64-bit
525515
/// register zeroed out. In other words, the result of MI has been explicitly
526516
/// zero extended.

‎llvm/utils/TableGen/GlobalISelEmitter.cpp

Copy file name to clipboardExpand all lines: llvm/utils/TableGen/GlobalISelEmitter.cpp
+1-2Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1115,9 +1115,8 @@ Error GlobalISelEmitter::importChildMatcher(
11151115
for (const TreePredicateCall &Call : SrcChild.getPredicateCalls()) {
11161116
const TreePredicateFn &Predicate = Call.Fn;
11171117

1118-
if (!Predicate.hasGISelLeafPredicateCode()) {
1118+
if (!Predicate.hasGISelLeafPredicateCode())
11191119
return failedImport("Src pattern child has unsupported predicate");
1120-
}
11211120
OM.addPredicate<OperandLeafPredicateMatcher>(Predicate);
11221121
}
11231122
return Error::success();

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