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Commit b92d165

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author
Aman Sharma
committed
added clang-format output
1 parent 515510f commit b92d165
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5 files changed

+150
-12
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‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Copy file name to clipboardExpand all lines: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+1-2
Original file line numberDiff line numberDiff line change
@@ -7047,7 +7047,6 @@ bool AMDGPULegalizerInfo::legalizeDebugTrap(MachineInstr &MI,
70477047
return true;
70487048
}
70497049

7050-
70517050
bool AMDGPULegalizerInfo::legalizeUbsanTrap(MachineInstr &MI,
70527051
MachineRegisterInfo &MRI,
70537052
MachineIRBuilder &B) const {
@@ -7058,7 +7057,7 @@ bool AMDGPULegalizerInfo::legalizeUbsanTrap(MachineInstr &MI,
70587057
DiagnosticInfoUnsupported NoTrap(B.getMF().getFunction(),
70597058
"ubsantrap handler not supported",
70607059
MI.getDebugLoc(), DS_Warning);
7061-
LLVMContext &Ctx = B.getMF().getFunction().getContext();
7060+
LLVMContext &Ctx = B.getContext();
70627061
Ctx.diagnose(NoTrap);
70637062
} else {
70647063
// Insert trap instruction

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h

Copy file name to clipboardExpand all lines: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
+1-3
Original file line numberDiff line numberDiff line change
@@ -244,10 +244,8 @@ class AMDGPULegalizerInfo final : public LegalizerInfo {
244244
bool legalizeDebugTrap(MachineInstr &MI, MachineRegisterInfo &MRI,
245245
MachineIRBuilder &B) const;
246246

247-
248247
bool legalizeUbsanTrap(MachineInstr &MI, MachineRegisterInfo &MRI,
249-
MachineIRBuilder &B) const;
250-
248+
MachineIRBuilder &B) const;
251249

252250
bool legalizeIntrinsic(LegalizerHelper &Helper,
253251
MachineInstr &MI) const override;

‎llvm/test/CodeGen/AMDGPU/trap-abis.ll

Copy file name to clipboardExpand all lines: llvm/test/CodeGen/AMDGPU/trap-abis.ll
+129
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@
88

99
declare void @llvm.trap() #0
1010
declare void @llvm.debugtrap() #1
11+
declare void @llvm.ubsantrap(i8) #2
1112

1213
define amdgpu_kernel void @trap(ptr addrspace(1) nocapture readonly %arg0) {
1314
; NOHSA-TRAP-GFX900-LABEL: trap:
@@ -482,6 +483,134 @@ define amdgpu_kernel void @debugtrap(ptr addrspace(1) nocapture readonly %arg0)
482483
ret void
483484
}
484485

486+
define void @ubsan_trap(ptr addrspace(1) nocapture readonly %arg0) {
487+
; CHECK-LABEL: ubsan_trap:
488+
; CHECK: ; %bb.0:
489+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
490+
; CHECK-NEXT: s_trap 2
491+
; CHECK-NEXT: s_setpc_b64 s[30:31]
492+
; NOHSA-TRAP-GFX900-LABEL: ubsan_trap:
493+
; NOHSA-TRAP-GFX900: ; %bb.0:
494+
; NOHSA-TRAP-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
495+
; NOHSA-TRAP-GFX900-NEXT: v_mov_b32_e32 v2, 1
496+
; NOHSA-TRAP-GFX900-NEXT: global_store_dword v[0:1], v2, off
497+
; NOHSA-TRAP-GFX900-NEXT: s_waitcnt vmcnt(0)
498+
; NOHSA-TRAP-GFX900-NEXT: s_cbranch_execnz .LBB4_2
499+
; NOHSA-TRAP-GFX900-NEXT: ; %bb.1:
500+
; NOHSA-TRAP-GFX900-NEXT: v_mov_b32_e32 v2, 2
501+
; NOHSA-TRAP-GFX900-NEXT: global_store_dword v[0:1], v2, off
502+
; NOHSA-TRAP-GFX900-NEXT: s_waitcnt vmcnt(0)
503+
; NOHSA-TRAP-GFX900-NEXT: s_setpc_b64 s[30:31]
504+
; NOHSA-TRAP-GFX900-NEXT: .LBB4_2:
505+
; NOHSA-TRAP-GFX900-NEXT: s_endpgm
506+
;
507+
; HSA-TRAP-GFX803-LABEL: ubsan_trap:
508+
; HSA-TRAP-GFX803: ; %bb.0:
509+
; HSA-TRAP-GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
510+
; HSA-TRAP-GFX803-NEXT: v_mov_b32_e32 v2, 1
511+
; HSA-TRAP-GFX803-NEXT: flat_store_dword v[0:1], v2
512+
; HSA-TRAP-GFX803-NEXT: s_waitcnt vmcnt(0)
513+
; HSA-TRAP-GFX803-NEXT: v_mov_b32_e32 v2, 2
514+
; HSA-TRAP-GFX803-NEXT: s_mov_b64 s[0:1], s[6:7]
515+
; HSA-TRAP-GFX803-NEXT: s_trap 2
516+
; HSA-TRAP-GFX803-NEXT: flat_store_dword v[0:1], v2
517+
; HSA-TRAP-GFX803-NEXT: s_waitcnt vmcnt(0)
518+
; HSA-TRAP-GFX803-NEXT: s_setpc_b64 s[30:31]
519+
;
520+
; HSA-TRAP-GFX900-LABEL: ubsan_trap:
521+
; HSA-TRAP-GFX900: ; %bb.0:
522+
; HSA-TRAP-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
523+
; HSA-TRAP-GFX900-NEXT: v_mov_b32_e32 v2, 1
524+
; HSA-TRAP-GFX900-NEXT: global_store_dword v[0:1], v2, off
525+
; HSA-TRAP-GFX900-NEXT: s_waitcnt vmcnt(0)
526+
; HSA-TRAP-GFX900-NEXT: v_mov_b32_e32 v2, 2
527+
; HSA-TRAP-GFX900-NEXT: s_trap 2
528+
; HSA-TRAP-GFX900-NEXT: global_store_dword v[0:1], v2, off
529+
; HSA-TRAP-GFX900-NEXT: s_waitcnt vmcnt(0)
530+
; HSA-TRAP-GFX900-NEXT: s_setpc_b64 s[30:31]
531+
;
532+
; HSA-NOTRAP-GFX900-LABEL: ubsan_trap:
533+
; HSA-NOTRAP-GFX900: ; %bb.0:
534+
; HSA-NOTRAP-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
535+
; HSA-NOTRAP-GFX900-NEXT: v_mov_b32_e32 v2, 1
536+
; HSA-NOTRAP-GFX900-NEXT: global_store_dword v[0:1], v2, off
537+
; HSA-NOTRAP-GFX900-NEXT: s_waitcnt vmcnt(0)
538+
; HSA-NOTRAP-GFX900-NEXT: s_cbranch_execnz .LBB4_2
539+
; HSA-NOTRAP-GFX900-NEXT: ; %bb.1:
540+
; HSA-NOTRAP-GFX900-NEXT: v_mov_b32_e32 v2, 2
541+
; HSA-NOTRAP-GFX900-NEXT: global_store_dword v[0:1], v2, off
542+
; HSA-NOTRAP-GFX900-NEXT: s_waitcnt vmcnt(0)
543+
; HSA-NOTRAP-GFX900-NEXT: s_setpc_b64 s[30:31]
544+
; HSA-NOTRAP-GFX900-NEXT: .LBB4_2:
545+
; HSA-NOTRAP-GFX900-NEXT: s_endpgm
546+
;
547+
; HSA-TRAP-GFX1100-LABEL: ubsan_trap:
548+
; HSA-TRAP-GFX1100: ; %bb.0:
549+
; HSA-TRAP-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
550+
; HSA-TRAP-GFX1100-NEXT: v_mov_b32_e32 v2, 1
551+
; HSA-TRAP-GFX1100-NEXT: global_store_b32 v[0:1], v2, off dlc
552+
; HSA-TRAP-GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
553+
; HSA-TRAP-GFX1100-NEXT: s_cbranch_execnz .LBB4_2
554+
; HSA-TRAP-GFX1100-NEXT: ; %bb.1:
555+
; HSA-TRAP-GFX1100-NEXT: v_mov_b32_e32 v2, 2
556+
; HSA-TRAP-GFX1100-NEXT: global_store_b32 v[0:1], v2, off dlc
557+
; HSA-TRAP-GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
558+
; HSA-TRAP-GFX1100-NEXT: s_setpc_b64 s[30:31]
559+
; HSA-TRAP-GFX1100-NEXT: .LBB4_2:
560+
; HSA-TRAP-GFX1100-NEXT: s_trap 2
561+
; HSA-TRAP-GFX1100-NEXT: s_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)
562+
; HSA-TRAP-GFX1100-NEXT: s_mov_b32 ttmp2, m0
563+
; HSA-TRAP-GFX1100-NEXT: s_waitcnt lgkmcnt(0)
564+
; HSA-TRAP-GFX1100-NEXT: s_and_b32 s0, s0, 0x3ff
565+
; HSA-TRAP-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
566+
; HSA-TRAP-GFX1100-NEXT: s_bitset1_b32 s0, 10
567+
; HSA-TRAP-GFX1100-NEXT: s_mov_b32 m0, s0
568+
; HSA-TRAP-GFX1100-NEXT: s_sendmsg sendmsg(MSG_INTERRUPT)
569+
; HSA-TRAP-GFX1100-NEXT: s_mov_b32 m0, ttmp2
570+
; HSA-TRAP-GFX1100-NEXT: .LBB4_3: ; =>This Inner Loop Header: Depth=1
571+
; HSA-TRAP-GFX1100-NEXT: s_sethalt 5
572+
; HSA-TRAP-GFX1100-NEXT: s_branch .LBB4_3
573+
;
574+
; HSA-TRAP-GFX1100-O0-LABEL: ubsan_trap:
575+
; HSA-TRAP-GFX1100-O0: ; %bb.0:
576+
; HSA-TRAP-GFX1100-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
577+
; HSA-TRAP-GFX1100-O0-NEXT: v_mov_b32_e32 v2, v1
578+
; HSA-TRAP-GFX1100-O0-NEXT: ; implicit-def: $sgpr0
579+
; HSA-TRAP-GFX1100-O0-NEXT: ; implicit-def: $sgpr0
580+
; HSA-TRAP-GFX1100-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec
581+
; HSA-TRAP-GFX1100-O0-NEXT: v_mov_b32_e32 v1, v2
582+
; HSA-TRAP-GFX1100-O0-NEXT: scratch_store_b64 off, v[0:1], s32 ; 8-byte Folded Spill
583+
; HSA-TRAP-GFX1100-O0-NEXT: ; implicit-def: $sgpr0_sgpr1
584+
; HSA-TRAP-GFX1100-O0-NEXT: v_mov_b32_e32 v2, 1
585+
; HSA-TRAP-GFX1100-O0-NEXT: global_store_b32 v[0:1], v2, off dlc
586+
; HSA-TRAP-GFX1100-O0-NEXT: s_waitcnt_vscnt null, 0x0
587+
; HSA-TRAP-GFX1100-O0-NEXT: s_cbranch_execnz .LBB4_2
588+
; HSA-TRAP-GFX1100-O0-NEXT: ; %bb.1:
589+
; HSA-TRAP-GFX1100-O0-NEXT: scratch_load_b64 v[0:1], off, s32 ; 8-byte Folded Reload
590+
; HSA-TRAP-GFX1100-O0-NEXT: v_mov_b32_e32 v2, 2
591+
; HSA-TRAP-GFX1100-O0-NEXT: s_waitcnt vmcnt(0)
592+
; HSA-TRAP-GFX1100-O0-NEXT: global_store_b32 v[0:1], v2, off dlc
593+
; HSA-TRAP-GFX1100-O0-NEXT: s_waitcnt_vscnt null, 0x0
594+
; HSA-TRAP-GFX1100-O0-NEXT: s_setpc_b64 s[30:31]
595+
; HSA-TRAP-GFX1100-O0-NEXT: .LBB4_2:
596+
; HSA-TRAP-GFX1100-O0-NEXT: s_trap 2
597+
; HSA-TRAP-GFX1100-O0-NEXT: s_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL)
598+
; HSA-TRAP-GFX1100-O0-NEXT: s_mov_b32 ttmp2, m0
599+
; HSA-TRAP-GFX1100-O0-NEXT: s_waitcnt lgkmcnt(0)
600+
; HSA-TRAP-GFX1100-O0-NEXT: s_and_b32 s0, s0, 0x3ff
601+
; HSA-TRAP-GFX1100-O0-NEXT: s_or_b32 s0, s0, 0x400
602+
; HSA-TRAP-GFX1100-O0-NEXT: s_mov_b32 m0, s0
603+
; HSA-TRAP-GFX1100-O0-NEXT: s_sendmsg sendmsg(MSG_INTERRUPT)
604+
; HSA-TRAP-GFX1100-O0-NEXT: s_mov_b32 m0, ttmp2
605+
; HSA-TRAP-GFX1100-O0-NEXT: .LBB4_3: ; =>This Inner Loop Header: Depth=1
606+
; HSA-TRAP-GFX1100-O0-NEXT: s_sethalt 5
607+
; HSA-TRAP-GFX1100-O0-NEXT: s_branch .LBB4_3
608+
store volatile i32 1, ptr addrspace(1) %arg0
609+
call void @llvm.ubsantrap(i8 0)
610+
store volatile i32 2, ptr addrspace(1) %arg0
611+
ret void
612+
}
613+
485614
attributes #0 = { nounwind noreturn }
486615
attributes #1 = { nounwind }
487616

‎llvm/test/CodeGen/AMDGPU/trap.ll

Copy file name to clipboardExpand all lines: llvm/test/CodeGen/AMDGPU/trap.ll
+19
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,4 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --function ubsantrap --version 5
12
; RUN: llc -global-isel=0 -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s
23
; RUN: llc -global-isel=1 -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s
34

@@ -28,6 +29,7 @@
2829

2930
declare void @llvm.trap() #0
3031
declare void @llvm.debugtrap() #1
32+
declare void @llvm.ubsantrap(i8) #2
3133

3234
; MESA-TRAP: .section .AMDGPU.config
3335
; MESA-TRAP: .long 47180
@@ -83,6 +85,13 @@ define amdgpu_kernel void @hsa_debugtrap(ptr addrspace(1) nocapture readonly %ar
8385
ret void
8486
}
8587

88+
define amdgpu_kernel void @ubsantrap(ptr addrspace(1) nocapture readonly %arg0) {
89+
store volatile i32 1, ptr addrspace(1) %arg0
90+
call void @llvm.ubsantrap(i8 0)
91+
store volatile i32 2, ptr addrspace(1) %arg0
92+
ret void
93+
}
94+
8695
; For non-HSA path
8796
; GCN-LABEL: {{^}}trap:
8897
; TRAP-BIT: enable_trap_handler = 1
@@ -147,3 +156,13 @@ attributes #1 = { nounwind }
147156

148157
!llvm.module.flags = !{!0}
149158
!0 = !{i32 1, !"amdhsa_code_object_version", i32 400}
159+
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
160+
; GCN: {{.*}}
161+
; GCN-WARNING: {{.*}}
162+
; HSA-TRAP: {{.*}}
163+
; MESA-TRAP: {{.*}}
164+
; NO-HSA-TRAP: {{.*}}
165+
; NO-MESA-TRAP: {{.*}}
166+
; NO-TRAP-BIT: {{.*}}
167+
; NOMESA-TRAP: {{.*}}
168+
; TRAP-BIT: {{.*}}

‎llvm/test/CodeGen/AMDGPU/ubsan_trap.ll

Copy file name to clipboardExpand all lines: llvm/test/CodeGen/AMDGPU/ubsan_trap.ll
-7
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