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Commit 99e8d22

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el-evel-ev
authored
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
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-36
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‎llvm/lib/Target/RISCV/RISCVInstrInfoQ.td

Copy file name to clipboardExpand all lines: llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
+57-35Lines changed: 57 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -25,97 +25,119 @@ defvar QExtsRV64 = [QExt];
2525
//===----------------------------------------------------------------------===//
2626

2727
let Predicates = [HasStdExtQ] in {
28-
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
29-
def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$rd),
30-
(ins GPRMem:$rs1, simm12:$imm12), "flq",
31-
"$rd, ${imm12}(${rs1})">;
28+
def FLQ : FPLoad_r<0b100, "flq", FPR128, WriteFLD128>;
29+
3230
// Operands for stores are in the order srcreg, base, offset rather than
3331
// reflecting the order these fields are specified in the instruction
3432
// encoding.
35-
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
36-
def FSQ : RVInstS<0b100, OPC_STORE_FP, (outs),
37-
(ins FPR128:$rs2, GPRMem:$rs1, simm12:$imm12), "fsq",
38-
"$rs2, ${imm12}(${rs1})">;
33+
def FSQ : FPStore_r<0b100, "fsq", FPR128, WriteFST128>;
3934
} // Predicates = [HasStdExtQ]
4035

4136
foreach Ext = QExts in {
42-
defm FMADD_Q : FPFMA_rrr_frm_m<OPC_MADD, 0b11, "fmadd.q", Ext>;
43-
defm FMSUB_Q : FPFMA_rrr_frm_m<OPC_MSUB, 0b11, "fmsub.q", Ext>;
44-
defm FNMSUB_Q : FPFMA_rrr_frm_m<OPC_NMSUB, 0b11, "fnmsub.q", Ext>;
45-
defm FNMADD_Q : FPFMA_rrr_frm_m<OPC_NMADD, 0b11, "fnmadd.q", Ext>;
37+
let SchedRW = [WriteFMA128, ReadFMA128, ReadFMA128, ReadFMA128Addend] in {
38+
defm FMADD_Q : FPFMA_rrr_frm_m<OPC_MADD, 0b11, "fmadd.q", Ext>;
39+
defm FMSUB_Q : FPFMA_rrr_frm_m<OPC_MSUB, 0b11, "fmsub.q", Ext>;
40+
defm FNMSUB_Q : FPFMA_rrr_frm_m<OPC_NMSUB, 0b11, "fnmsub.q", Ext>;
41+
defm FNMADD_Q : FPFMA_rrr_frm_m<OPC_NMADD, 0b11, "fnmadd.q", Ext>;
42+
}
4643

47-
defm FADD_Q : FPALU_rr_frm_m<0b0000011, "fadd.q", Ext>;
48-
defm FSUB_Q : FPALU_rr_frm_m<0b0000111, "fsub.q", Ext>;
44+
let SchedRW = [WriteFAdd128, ReadFAdd128, ReadFAdd128] in {
45+
defm FADD_Q : FPALU_rr_frm_m<0b0000011, "fadd.q", Ext>;
46+
defm FSUB_Q : FPALU_rr_frm_m<0b0000111, "fsub.q", Ext>;
47+
}
4948

49+
let SchedRW = [WriteFMul128, ReadFMul128, ReadFMul128] in
5050
defm FMUL_Q : FPALU_rr_frm_m<0b0001011, "fmul.q", Ext>;
5151

52+
let SchedRW = [WriteFDiv128, ReadFDiv128, ReadFDiv128] in
5253
defm FDIV_Q : FPALU_rr_frm_m<0b0001111, "fdiv.q", Ext>;
5354

5455
defm FSQRT_Q : FPUnaryOp_r_frm_m<0b0101111, 0b00000, Ext, Ext.PrimaryTy,
55-
Ext.PrimaryTy, "fsqrt.q">;
56+
Ext.PrimaryTy, "fsqrt.q">,
57+
Sched<[WriteFSqrt128, ReadFSqrt128]>;
5658

57-
let mayRaiseFPException = 0 in {
59+
let SchedRW = [WriteFSGNJ128, ReadFSGNJ128, ReadFSGNJ128],
60+
mayRaiseFPException = 0 in {
5861
defm FSGNJ_Q : FPALU_rr_m<0b0010011, 0b000, "fsgnj.q", Ext>;
5962
defm FSGNJN_Q : FPALU_rr_m<0b0010011, 0b001, "fsgnjn.q", Ext>;
6063
defm FSGNJX_Q : FPALU_rr_m<0b0010011, 0b010, "fsgnjx.q", Ext>;
6164
}
6265

63-
defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
64-
defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
66+
let SchedRW = [WriteFMinMax128, ReadFMinMax128, ReadFMinMax128] in {
67+
defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
68+
defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
69+
}
6570

6671
defm FCVT_S_Q : FPUnaryOp_r_frm_m<0b0100000, 0b00011, Ext, Ext.F32Ty,
67-
Ext.PrimaryTy, "fcvt.s.q">;
72+
Ext.PrimaryTy, "fcvt.s.q">,
73+
Sched<[WriteFCvtF128ToF32, ReadFCvtF128ToF32]>;
6874

6975
defm FCVT_Q_S : FPUnaryOp_r_frmlegacy_m<0b0100011, 0b00000, Ext,
70-
Ext.PrimaryTy, Ext.F32Ty, "fcvt.q.s">;
76+
Ext.PrimaryTy, Ext.F32Ty,
77+
"fcvt.q.s">,
78+
Sched<[WriteFCvtF32ToF128, ReadFCvtF32ToF128]>;
7179

7280
defm FCVT_D_Q : FPUnaryOp_r_frm_m<0b0100001, 0b00011, Ext, Ext.F64Ty,
73-
Ext.PrimaryTy, "fcvt.d.q">;
81+
Ext.PrimaryTy, "fcvt.d.q">,
82+
Sched<[WriteFCvtF128ToF64, ReadFCvtF128ToF64]>;
7483

7584
defm FCVT_Q_D : FPUnaryOp_r_frmlegacy_m<0b0100011, 0b00001, Ext,
76-
Ext.PrimaryTy, Ext.F64Ty, "fcvt.q.d">;
77-
78-
defm FEQ_Q : FPCmp_rr_m<0b1010011, 0b010, "feq.q", Ext, Commutable = 1>;
79-
defm FLT_Q : FPCmp_rr_m<0b1010011, 0b001, "flt.q", Ext>;
80-
defm FLE_Q : FPCmp_rr_m<0b1010011, 0b000, "fle.q", Ext>;
85+
Ext.PrimaryTy, Ext.F64Ty,
86+
"fcvt.q.d">,
87+
Sched<[WriteFCvtF64ToF128, ReadFCvtF64ToF128]>;
88+
89+
let SchedRW = [WriteFCmp128, ReadFCmp128, ReadFCmp128] in {
90+
defm FEQ_Q : FPCmp_rr_m<0b1010011, 0b010, "feq.q", Ext, Commutable = 1>;
91+
defm FLT_Q : FPCmp_rr_m<0b1010011, 0b001, "flt.q", Ext>;
92+
defm FLE_Q : FPCmp_rr_m<0b1010011, 0b000, "fle.q", Ext>;
93+
}
8194

8295
let mayRaiseFPException = 0 in
8396
defm FCLASS_Q : FPUnaryOp_r_m<0b1110011, 0b00000, 0b001, Ext, GPR,
84-
Ext.PrimaryTy, "fclass.q">;
97+
Ext.PrimaryTy, "fclass.q">,
98+
Sched<[WriteFClass128, ReadFClass128]>;
8599

86100
let IsSignExtendingOpW = 1 in
87101
defm FCVT_W_Q : FPUnaryOp_r_frm_m<0b1100011, 0b00000, Ext, GPR,
88-
Ext.PrimaryTy, "fcvt.w.q">;
102+
Ext.PrimaryTy, "fcvt.w.q">,
103+
Sched<[WriteFCvtF128ToI32, ReadFCvtF128ToI32]>;
89104

90105
let IsSignExtendingOpW = 1 in
91106
defm FCVT_WU_Q : FPUnaryOp_r_frm_m<0b1100011, 0b00001, Ext, GPR,
92-
Ext.PrimaryTy, "fcvt.wu.q">;
107+
Ext.PrimaryTy, "fcvt.wu.q">,
108+
Sched<[WriteFCvtF128ToI32, ReadFCvtF128ToI32]>;
93109

94110
let mayRaiseFPException = 0 in
95111
defm FCVT_Q_W : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00000, Ext,
96-
Ext.PrimaryTy, GPR, "fcvt.q.w">;
112+
Ext.PrimaryTy, GPR, "fcvt.q.w">,
113+
Sched<[WriteFCvtI32ToF128, ReadFCvtI32ToF128]>;
97114

98115
let mayRaiseFPException = 0 in
99116
defm FCVT_Q_WU : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00001, Ext,
100-
Ext.PrimaryTy, GPR, "fcvt.q.wu">;
117+
Ext.PrimaryTy, GPR, "fcvt.q.wu">,
118+
Sched<[WriteFCvtI32ToF128, ReadFCvtI32ToF128]>;
101119
} // foreach Ext = QExts
102120

103121
foreach Ext = QExtsRV64 in {
104122
defm FCVT_L_Q : FPUnaryOp_r_frm_m<0b1100011, 0b00010, Ext, GPR,
105-
Ext.PrimaryTy, "fcvt.l.q", [IsRV64]>;
123+
Ext.PrimaryTy, "fcvt.l.q", [IsRV64]>,
124+
Sched<[WriteFCvtF128ToI64, ReadFCvtF128ToI64]>;
106125

107126
defm FCVT_LU_Q : FPUnaryOp_r_frm_m<0b1100011, 0b00011, Ext, GPR,
108-
Ext.PrimaryTy, "fcvt.lu.q", [IsRV64]>;
127+
Ext.PrimaryTy, "fcvt.lu.q", [IsRV64]>,
128+
Sched<[WriteFCvtF128ToI64, ReadFCvtF128ToI64]>;
109129

110130
let mayRaiseFPException = 0 in
111131
defm FCVT_Q_L : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00010, Ext,
112132
Ext.PrimaryTy, GPR, "fcvt.q.l",
113-
[IsRV64]>;
133+
[IsRV64]>,
134+
Sched<[WriteFCvtI64ToF128, ReadFCvtI64ToF128]>;
114135

115136
let mayRaiseFPException = 0 in
116137
defm FCVT_Q_LU : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00011, Ext,
117138
Ext.PrimaryTy, GPR, "fcvt.q.lu",
118-
[IsRV64]>;
139+
[IsRV64]>,
140+
Sched<[WriteFCvtI64ToF128, ReadFCvtI64ToF128]>;
119141
} // foreach Ext = QExtsRV64
120142

121143
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td

Copy file name to clipboardExpand all lines: llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td
+1Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -492,6 +492,7 @@ def : ReadAdvance<ReadFSqrt16, 0>;
492492
//===----------------------------------------------------------------------===//
493493
// Unsupported extensions
494494
//===----------------------------------------------------------------------===//
495+
defm : UnsupportedSchedQ;
495496
defm : UnsupportedSchedV;
496497
defm : UnsupportedSchedZvk;
497498
defm : UnsupportedSchedSFB;

‎llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td

Copy file name to clipboardExpand all lines: llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
+1Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -263,6 +263,7 @@ def : ReadAdvance<ReadIRem, 0>;
263263
def : ReadAdvance<ReadIRem32, 0>;
264264

265265
// Unsupported extensions.
266+
defm : UnsupportedSchedQ;
266267
defm : UnsupportedSchedV;
267268
defm : UnsupportedSchedZbc;
268269
defm : UnsupportedSchedZbs;

‎llvm/lib/Target/RISCV/RISCVSchedRocket.td

Copy file name to clipboardExpand all lines: llvm/lib/Target/RISCV/RISCVSchedRocket.td
+1Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -250,6 +250,7 @@ def : ReadAdvance<ReadFClass64, 0>;
250250

251251
//===----------------------------------------------------------------------===//
252252
// Unsupported extensions
253+
defm : UnsupportedSchedQ;
253254
defm : UnsupportedSchedV;
254255
defm : UnsupportedSchedZabha;
255256
defm : UnsupportedSchedZba;

‎llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

Copy file name to clipboardExpand all lines: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+1Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1300,6 +1300,7 @@ foreach mx = SchedMxList in {
13001300

13011301
//===----------------------------------------------------------------------===//
13021302
// Unsupported extensions
1303+
defm : UnsupportedSchedQ;
13031304
defm : UnsupportedSchedZabha;
13041305
defm : UnsupportedSchedZbc;
13051306
defm : UnsupportedSchedZbkb;

‎llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td

Copy file name to clipboardExpand all lines: llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
+1Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1231,6 +1231,7 @@ defm "" : LMULReadAdvance<"ReadVSM3MEV", 0>;
12311231

12321232
//===----------------------------------------------------------------------===//
12331233
// Unsupported extensions
1234+
defm : UnsupportedSchedQ;
12341235
defm : UnsupportedSchedZabha;
12351236
defm : UnsupportedSchedZbc;
12361237
defm : UnsupportedSchedZbkb;

‎llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td

Copy file name to clipboardExpand all lines: llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td
+1Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -348,6 +348,7 @@ def : ReadAdvance<ReadSHXADD32, 0>;
348348

349349
//===----------------------------------------------------------------------===//
350350
// Unsupported extensions
351+
defm : UnsupportedSchedQ;
351352
defm : UnsupportedSchedV;
352353
defm : UnsupportedSchedZabha;
353354
defm : UnsupportedSchedZbc;

‎llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td

Copy file name to clipboardExpand all lines: llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
+1Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1487,6 +1487,7 @@ defm "" : LMULReadAdvance<"ReadVSM3MEV", 0>;
14871487

14881488
//===----------------------------------------------------------------------===//
14891489
// Unsupported extensions
1490+
defm : UnsupportedSchedQ;
14901491
defm : UnsupportedSchedZabha;
14911492
defm : UnsupportedSchedZbc;
14921493
defm : UnsupportedSchedZbkb;

‎llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td

Copy file name to clipboardExpand all lines: llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
+1Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -342,6 +342,7 @@ def : ReadAdvance<ReadSingleBitImm, 0>;
342342

343343
//===----------------------------------------------------------------------===//
344344
// Unsupported extensions
345+
defm : UnsupportedSchedQ;
345346
defm : UnsupportedSchedV;
346347
defm : UnsupportedSchedXsfvcp;
347348
defm : UnsupportedSchedZabha;

‎llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td

Copy file name to clipboardExpand all lines: llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td
+1Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -199,6 +199,7 @@ multiclass SCR3_Unsupported :
199199

200200
multiclass SCR4_SCR5_Unsupported :
201201
SCR_Unsupported,
202+
UnsupportedSchedQ,
202203
UnsupportedSchedZfhmin;
203204

204205
// Bypasses (none)

‎llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td

Copy file name to clipboardExpand all lines: llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td
+1Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -241,6 +241,7 @@ multiclass SCR7_Other {
241241

242242
// Unsupported scheduling classes for SCR7.
243243
multiclass SCR7_Unsupported {
244+
defm : UnsupportedSchedQ;
244245
defm : UnsupportedSchedSFB;
245246
defm : UnsupportedSchedV;
246247
defm : UnsupportedSchedXsfvcp;

‎llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td

Copy file name to clipboardExpand all lines: llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
+1Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -318,6 +318,7 @@ def : ReadAdvance<ReadSingleBitImm, 0>;
318318

319319
//===----------------------------------------------------------------------===//
320320
// Unsupported extensions
321+
defm : UnsupportedSchedQ;
321322
defm : UnsupportedSchedV;
322323
defm : UnsupportedSchedXsfvcp;
323324
defm : UnsupportedSchedZabha;

‎llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td

Copy file name to clipboardExpand all lines: llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
+1Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -306,6 +306,7 @@ def : ReadAdvance<ReadXPERM, 0>;
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307307
//===----------------------------------------------------------------------===//
308308
// Unsupported extensions
309+
defm : UnsupportedSchedQ;
309310
defm : UnsupportedSchedV;
310311
defm : UnsupportedSchedZfa;
311312
defm : UnsupportedSchedZfhmin;

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