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Commit 4c9fca9

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author
Dan Gohman
committed
Remove the Alpha backend.
llvm-svn: 143164
1 parent f211416 commit 4c9fca9
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‎llvm/CMakeLists.txt‎

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-1Lines changed: 0 additions & 1 deletion
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@@ -64,7 +64,6 @@ Please clean the source directory.")
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endif()
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set(LLVM_ALL_TARGETS
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Alpha
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ARM
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CBackend
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CellSPU
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‎llvm/autoconf/configure.ac‎

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+2-6Lines changed: 2 additions & 6 deletions
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@@ -352,7 +352,6 @@ AC_CACHE_CHECK([target architecture],[llvm_cv_target_arch],
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amd64-* | x86_64-*) llvm_cv_target_arch="x86_64" ;;
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sparc*-*) llvm_cv_target_arch="Sparc" ;;
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powerpc*-*) llvm_cv_target_arch="PowerPC" ;;
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alpha*-*) llvm_cv_target_arch="Alpha" ;;
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arm*-*) llvm_cv_target_arch="ARM" ;;
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mips-*) llvm_cv_target_arch="Mips" ;;
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xcore-*) llvm_cv_target_arch="XCore" ;;
@@ -487,7 +486,6 @@ else
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Sparc) AC_SUBST(TARGET_HAS_JIT,0) ;;
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PowerPC) AC_SUBST(TARGET_HAS_JIT,1) ;;
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x86_64) AC_SUBST(TARGET_HAS_JIT,1) ;;
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Alpha) AC_SUBST(TARGET_HAS_JIT,0) ;;
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ARM) AC_SUBST(TARGET_HAS_JIT,1) ;;
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Mips) AC_SUBST(TARGET_HAS_JIT,1) ;;
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XCore) AC_SUBST(TARGET_HAS_JIT,0) ;;
@@ -603,21 +601,20 @@ dnl Allow specific targets to be specified for building (or not)
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TARGETS_TO_BUILD=""
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AC_ARG_ENABLE([targets],AS_HELP_STRING([--enable-targets],
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[Build specific host targets: all or target1,target2,... Valid targets are:
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host, x86, x86_64, sparc, powerpc, alpha, arm, mips, spu,
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host, x86, x86_64, sparc, powerpc, arm, mips, spu,
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xcore, msp430, ptx, cbe, and cpp (default=all)]),,
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enableval=all)
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if test "$enableval" = host-only ; then
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enableval=host
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fi
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case "$enableval" in
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all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
611+
all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
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*)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
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case "$a_target" in
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x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
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x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
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sparc) TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
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powerpc) TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
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alpha) TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
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arm) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
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mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
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spu) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
@@ -632,7 +629,6 @@ case "$enableval" in
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x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
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Sparc) TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
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PowerPC) TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
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Alpha) TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
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ARM) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
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Mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
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MBlaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
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‎llvm/cmake/config-ix.cmake‎

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@@ -309,8 +309,6 @@ elseif (LLVM_NATIVE_ARCH MATCHES "sparc")
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set(LLVM_NATIVE_ARCH Sparc)
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elseif (LLVM_NATIVE_ARCH MATCHES "powerpc")
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set(LLVM_NATIVE_ARCH PowerPC)
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elseif (LLVM_NATIVE_ARCH MATCHES "alpha")
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set(LLVM_NATIVE_ARCH Alpha)
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elseif (LLVM_NATIVE_ARCH MATCHES "arm")
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set(LLVM_NATIVE_ARCH ARM)
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elseif (LLVM_NATIVE_ARCH MATCHES "mips")
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‎llvm/configure‎

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+2-7Lines changed: 2 additions & 7 deletions
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@@ -1415,7 +1415,7 @@ Optional Features:
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(default is YES)
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--enable-targets Build specific host targets: all or
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target1,target2,... Valid targets are: host, x86,
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x86_64, sparc, powerpc, alpha, arm, mips, spu,
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x86_64, sparc, powerpc, arm, mips, spu,
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xcore, msp430, ptx, cbe, and cpp (default=all)
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--enable-cbe-printf-a Enable C Backend output with hex floating point via
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%a (default is YES)
@@ -3874,7 +3874,6 @@ else
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amd64-* | x86_64-*) llvm_cv_target_arch="x86_64" ;;
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sparc*-*) llvm_cv_target_arch="Sparc" ;;
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powerpc*-*) llvm_cv_target_arch="PowerPC" ;;
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alpha*-*) llvm_cv_target_arch="Alpha" ;;
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arm*-*) llvm_cv_target_arch="ARM" ;;
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mips-*) llvm_cv_target_arch="Mips" ;;
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xcore-*) llvm_cv_target_arch="XCore" ;;
@@ -5071,8 +5070,6 @@ else
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PowerPC) TARGET_HAS_JIT=1
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;;
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x86_64) TARGET_HAS_JIT=1
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;;
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Alpha) TARGET_HAS_JIT=0
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;;
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ARM) TARGET_HAS_JIT=1
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;;
@@ -5270,14 +5267,13 @@ if test "$enableval" = host-only ; then
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enableval=host
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fi
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case "$enableval" in
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all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
5270+
all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
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*)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
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case "$a_target" in
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x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
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x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
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sparc) TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
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powerpc) TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
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alpha) TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
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arm) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
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mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
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spu) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
@@ -5292,7 +5288,6 @@ case "$enableval" in
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x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
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Sparc) TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
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PowerPC) TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
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Alpha) TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
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ARM) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
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Mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
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MBlaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
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‎llvm/docs/CMake.html‎

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+1-1Lines changed: 1 addition & 1 deletion
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@@ -249,7 +249,7 @@ <h3>
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<dd>Semicolon-separated list of targets to build, or <i>all</i> for
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building all targets. Case-sensitive. For Visual C++ defaults
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to <i>X86</i>. On the other cases defaults to <i>all</i>. Example:
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<i>-DLLVM_TARGETS_TO_BUILD="X86;PowerPC;Alpha"</i>.</dd>
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<i>-DLLVM_TARGETS_TO_BUILD="X86;PowerPC"</i>.</dd>
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<dt><b>LLVM_BUILD_TOOLS</b>:BOOL</dt>
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<dd>Build LLVM tools. Defaults to ON. Targets for building each tool
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‎llvm/docs/CodeGenerator.html‎

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@@ -2208,7 +2208,6 @@ <h3>
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<tr>
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<th>Feature</th>
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<th>ARM</th>
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<th>Alpha</th>
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<th>CellSPU</th>
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<th>MBlaze</th>
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<th>MSP430</th>
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<tr>
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<td><a href="#feat_reliable">is generally reliable</a></td>
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<td class="yes"></td> <!-- ARM -->
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<td class="unknown"></td> <!-- Alpha -->
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<td class="no"></td> <!-- CellSPU -->
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<td class="no"></td> <!-- MBlaze -->
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<td class="unknown"></td> <!-- MSP430 -->
@@ -2238,7 +2236,6 @@ <h3>
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<tr>
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<td><a href="#feat_asmparser">assembly parser</a></td>
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<td class="no"></td> <!-- ARM -->
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<td class="no"></td> <!-- Alpha -->
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<td class="no"></td> <!-- CellSPU -->
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<td class="yes"></td> <!-- MBlaze -->
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<td class="no"></td> <!-- MSP430 -->
@@ -2253,7 +2250,6 @@ <h3>
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<tr>
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<td><a href="#feat_disassembler">disassembler</a></td>
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<td class="yes"></td> <!-- ARM -->
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<td class="no"></td> <!-- Alpha -->
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<td class="no"></td> <!-- CellSPU -->
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<td class="yes"></td> <!-- MBlaze -->
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<td class="no"></td> <!-- MSP430 -->
@@ -2268,7 +2264,6 @@ <h3>
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<tr>
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<td><a href="#feat_inlineasm">inline asm</a></td>
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<td class="yes"></td> <!-- ARM -->
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<td class="unknown"></td> <!-- Alpha -->
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<td class="no"></td> <!-- CellSPU -->
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<td class="yes"></td> <!-- MBlaze -->
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<td class="unknown"></td> <!-- MSP430 -->
@@ -2283,7 +2278,6 @@ <h3>
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<tr>
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<td><a href="#feat_jit">jit</a></td>
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<td class="partial"><a href="#feat_jit_arm">*</a></td> <!-- ARM -->
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<td class="no"></td> <!-- Alpha -->
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<td class="no"></td> <!-- CellSPU -->
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<td class="no"></td> <!-- MBlaze -->
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<td class="unknown"></td> <!-- MSP430 -->
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<tr>
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<td><a href="#feat_objectwrite">.o&nbsp;file writing</a></td>
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<td class="no"></td> <!-- ARM -->
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<td class="no"></td> <!-- Alpha -->
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<td class="no"></td> <!-- CellSPU -->
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<td class="yes"></td> <!-- MBlaze -->
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<td class="no"></td> <!-- MSP430 -->
@@ -2313,7 +2306,6 @@ <h3>
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<tr>
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<td><a href="#feat_tailcall">tail calls</a></td>
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<td class="yes"></td> <!-- ARM -->
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<td class="unknown"></td> <!-- Alpha -->
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<td class="no"></td> <!-- CellSPU -->
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<td class="no"></td> <!-- MBlaze -->
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<td class="unknown"></td> <!-- MSP430 -->
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‎llvm/docs/CompilerWriterInfo.html‎

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<ol>
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<li><a href="#hw">Hardware</a>
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<ol>
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<li><a href="#alpha">Alpha</a></li>
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<li><a href="#arm">ARM</a></li>
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<li><a href="#ia64">Itanium</a></li>
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<li><a href="#mips">MIPS</a></li>
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<div>
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<!-- ======================================================================= -->
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<h3><a name="alpha">Alpha</a></h3>
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<div>
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<ul>
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<li><a
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href="http://ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html">Alpha manuals</a>
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</li>
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</ul>
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</div>
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<!-- ======================================================================= -->
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<h3><a name="arm">ARM</a></h3>
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‎llvm/docs/UsingLibraries.html‎

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@@ -126,8 +126,6 @@ <h2><a name="descriptions">Library Descriptions</a></h2>
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<td>Aggressive instruction selector for directed acyclic graphs</td></tr>
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<tr><th colspan="3">Target Libraries</th></tr>
129-
<tr><td>LLVMAlpha</td><td><tt>.o</tt></td>
130-
<td>Code generation for Alpha architecture</td></tr>
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<tr><td>LLVMARM</td><td><tt>.o</tt></td>
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<td>Code generation for ARM architecture</td></tr>
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<tr><td>LLVMCBackend</td><td><tt>.o</tt></td>
@@ -333,14 +331,6 @@ <h3>Dependency Relationships Of Object Files</h3>
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<li>libLLVMSystem.a</li>
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<li>libLLVMTarget.a</li>
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</ul></dd>
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<dt><b>LLVMAlpha.o</b></dt><dd><ul>
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<li>libLLVMCodeGen.a</li>
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<li>libLLVMCore.a</li>
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<li>libLLVMSelectionDAG.a</li>
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<li>libLLVMSupport.a</li>
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</ul></dd>
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<dt><b>LLVMCBackend.o</b></dt><dd><ul>
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<li>libLLVMAnalysis.a</li>
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<li>libLLVMCodeGen.a</li>
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‎llvm/include/llvm/ADT/Triple.h‎

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@@ -43,7 +43,6 @@ class Triple {
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enum ArchType {
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UnknownArch,
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alpha, // Alpha: alpha
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arm, // ARM; arm, armv.*, xscale
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cellspu, // CellSPU: spu, cellspu
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mips, // MIPS: mips, mipsallegrex
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‎llvm/include/llvm/Intrinsics.td‎

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@@ -443,6 +443,5 @@ include "llvm/IntrinsicsPowerPC.td"
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include "llvm/IntrinsicsX86.td"
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include "llvm/IntrinsicsARM.td"
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include "llvm/IntrinsicsCellSPU.td"
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include "llvm/IntrinsicsAlpha.td"
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include "llvm/IntrinsicsXCore.td"
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include "llvm/IntrinsicsPTX.td"

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