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Commit 41892d8

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el-evel-ev
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release note
1 parent eb15367 commit 41892d8
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‎llvm/docs/ReleaseNotes.md

Copy file name to clipboardExpand all lines: llvm/docs/ReleaseNotes.md
+2Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -186,6 +186,8 @@ Changes to the RISC-V Backend
186186
* Adds assembler support for the Andes `XAndesperf` (Andes Performance extension).
187187
* `-mcpu=sifive-p870` was added.
188188
* Adds assembler support for the Andes `XAndesvpackfph` (Andes Vector Packed FP16 extension).
189+
* Adds assembler support for the standard `Q` (Quad-Precision Floating Point)
190+
extension.
189191

190192
Changes to the WebAssembly Backend
191193
----------------------------------

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Copy file name to clipboardExpand all lines: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
-13Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -599,13 +599,6 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
599599
return;
600600
}
601601

602-
if (RISCV::FPR128RegClass.contains(DstReg, SrcReg)) {
603-
BuildMI(MBB, MBBI, DL, get(RISCV::FSGNJ_Q), DstReg)
604-
.addReg(SrcReg, getKillRegState(KillSrc))
605-
.addReg(SrcReg, getKillRegState(KillSrc));
606-
return;
607-
}
608-
609602
if (RISCV::FPR32RegClass.contains(DstReg) &&
610603
RISCV::GPRRegClass.contains(SrcReg)) {
611604
BuildMI(MBB, MBBI, DL, get(RISCV::FMV_W_X), DstReg)
@@ -681,9 +674,6 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
681674
} else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) {
682675
Opcode = RISCV::FSD;
683676
IsScalableVector = false;
684-
} else if (RISCV::FPR128RegClass.hasSubClassEq(RC)) {
685-
Opcode = RISCV::FSQ;
686-
IsScalableVector = false;
687677
} else if (RISCV::VRRegClass.hasSubClassEq(RC)) {
688678
Opcode = RISCV::VS1R_V;
689679
} else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) {
@@ -776,9 +766,6 @@ void RISCVInstrInfo::loadRegFromStackSlot(
776766
} else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) {
777767
Opcode = RISCV::FLD;
778768
IsScalableVector = false;
779-
} else if (RISCV::FPR128RegClass.hasSubClassEq(RC)) {
780-
Opcode = RISCV::FLQ;
781-
IsScalableVector = false;
782769
} else if (RISCV::VRRegClass.hasSubClassEq(RC)) {
783770
Opcode = RISCV::VL1RE8_V;
784771
} else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) {

‎llvm/lib/Target/RISCV/RISCVInstrInfoQ.td

Copy file name to clipboardExpand all lines: llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
+12-18Lines changed: 12 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -27,15 +27,15 @@ defvar QExtsRV64 = [QExt];
2727
let Predicates = [HasStdExtQ] in {
2828
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
2929
def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$rd),
30-
(ins GPRMem:$rs1, simm12:$imm12),
31-
"flq", "$rd, ${imm12}(${rs1})">;
30+
(ins GPRMem:$rs1, simm12:$imm12), "flq",
31+
"$rd, ${imm12}(${rs1})">;
3232
// Operands for stores are in the order srcreg, base, offset rather than
3333
// reflecting the order these fields are specified in the instruction
3434
// encoding.
3535
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
3636
def FSQ : RVInstS<0b100, OPC_STORE_FP, (outs),
37-
(ins FPR128:$rs2, GPRMem:$rs1, simm12:$imm12),
38-
"fsq", "$rs2, ${imm12}(${rs1})">;
37+
(ins FPR128:$rs2, GPRMem:$rs1, simm12:$imm12), "fsq",
38+
"$rs2, ${imm12}(${rs1})">;
3939
} // Predicates = [HasStdExtQ]
4040

4141
foreach Ext = QExts in {
@@ -93,11 +93,11 @@ foreach Ext = QExts in {
9393

9494
let mayRaiseFPException = 0 in
9595
defm FCVT_Q_W : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00000, Ext,
96-
Ext.PrimaryTy, GPR, "fcvt.q.w">;
96+
Ext.PrimaryTy, GPR, "fcvt.q.w">;
9797

9898
let mayRaiseFPException = 0 in
9999
defm FCVT_Q_WU : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00001, Ext,
100-
Ext.PrimaryTy, GPR, "fcvt.q.wu">;
100+
Ext.PrimaryTy, GPR, "fcvt.q.wu">;
101101
} // foreach Ext = QExts
102102

103103
foreach Ext = QExtsRV64 in {
@@ -108,12 +108,14 @@ foreach Ext = QExtsRV64 in {
108108
Ext.PrimaryTy, "fcvt.lu.q", [IsRV64]>;
109109

110110
let mayRaiseFPException = 0 in
111-
defm FCVT_Q_L : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00010, Ext, Ext.PrimaryTy,
112-
GPR, "fcvt.q.l", [IsRV64]>;
111+
defm FCVT_Q_L : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00010, Ext,
112+
Ext.PrimaryTy, GPR, "fcvt.q.l",
113+
[IsRV64]>;
113114

114115
let mayRaiseFPException = 0 in
115-
defm FCVT_Q_LU : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00011, Ext, Ext.PrimaryTy,
116-
GPR, "fcvt.q.lu", [IsRV64]>;
116+
defm FCVT_Q_LU : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00011, Ext,
117+
Ext.PrimaryTy, GPR, "fcvt.q.lu",
118+
[IsRV64]>;
117119
} // foreach Ext = QExtsRV64
118120

119121
//===----------------------------------------------------------------------===//
@@ -141,11 +143,3 @@ let Predicates = [HasStdExtQ] in {
141143
def PseudoFLQ : PseudoFloatLoad<"flq", FPR128>;
142144
def PseudoFSQ : PseudoStore<"fsq", FPR128>;
143145
} // Predicates = [HasStdExtQ]
144-
145-
let Predicates = [HasStdExtQ] in {
146-
/// Loads
147-
def : LdPat<load, FLQ, f128>;
148-
149-
/// Stores
150-
def : StPat<store, FSQ, FPR128, f128>;
151-
} // Predicates = [HasStdExtQ]

‎llvm/lib/Target/RISCV/RISCVSubtarget.h

Copy file name to clipboardExpand all lines: llvm/lib/Target/RISCV/RISCVSubtarget.h
-3Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -198,9 +198,6 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
198198
bool useLoadStorePairs() const;
199199
bool useCCMovInsn() const;
200200
unsigned getFLen() const {
201-
if (HasStdExtQ)
202-
return 128;
203-
204201
if (HasStdExtD)
205202
return 64;
206203

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