@@ -10019,7 +10019,8 @@ SDValue DAGCombiner::visitShiftByConstant(SDNode *N) {
1001910019 BinOpLHSVal.getOpcode() == ISD::SRL) &&
1002010020 isa<ConstantSDNode>(BinOpLHSVal.getOperand(1));
1002110021 bool IsCopyOrSelect = BinOpLHSVal.getOpcode() == ISD::CopyFromReg ||
10022- BinOpLHSVal.getOpcode() == ISD::SELECT;
10022+ BinOpLHSVal.getOpcode() == ISD::SELECT ||
10023+ BinOpLHSVal.getOpcode() == ISD::VSELECT;
1002310024
1002410025 if (!IsShiftByConstant && !IsCopyOrSelect)
1002510026 return SDValue();
@@ -13437,7 +13438,7 @@ static SDValue tryToFoldExtendOfConstant(SDNode *N, const SDLoc &DL,
1343713438 // fold (sext (select cond, c1, c2)) -> (select cond, sext c1, sext c2)
1343813439 // fold (zext (select cond, c1, c2)) -> (select cond, zext c1, zext c2)
1343913440 // fold (aext (select cond, c1, c2)) -> (select cond, sext c1, sext c2)
13440- if (N0->getOpcode() == ISD::SELECT) {
13441+ if (N0->getOpcode() == ISD::SELECT || N0->getOpcode() == ISD::VSELECT ) {
1344113442 SDValue Op1 = N0->getOperand(1);
1344213443 SDValue Op2 = N0->getOperand(2);
1344313444 if (isa<ConstantSDNode>(Op1) && isa<ConstantSDNode>(Op2) &&
@@ -17765,10 +17766,11 @@ SDValue DAGCombiner::visitFMUL(SDNode *N) {
1776517766 // fold (fmul X, (select (fcmp X > 0.0), -1.0, 1.0)) -> (fneg (fabs X))
1776617767 // fold (fmul X, (select (fcmp X > 0.0), 1.0, -1.0)) -> (fabs X)
1776717768 if (Flags.hasNoNaNs() && Flags.hasNoSignedZeros() &&
17768- (N0.getOpcode() == ISD::SELECT || N1.getOpcode() == ISD::SELECT) &&
17769+ (N0.getOpcode() == ISD::SELECT || N0.getOpcode() == ISD::VSELECT ||
17770+ N1.getOpcode() == ISD::SELECT || N1.getOpcode() == ISD::VSELECT) &&
1776917771 TLI.isOperationLegal(ISD::FABS, VT)) {
1777017772 SDValue Select = N0, X = N1;
17771- if (Select.getOpcode() != ISD::SELECT)
17773+ if (Select.getOpcode() != ISD::SELECT && Select.getOpcode() != ISD::VSELECT )
1777217774 std::swap(Select, X);
1777317775
1777417776 SDValue Cond = Select.getOperand(0);
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