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Commit 109bc60

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[X86] Remove extra MOV after widening atomic load
This change adds patterns to optimize out an extra MOV present after widening the atomic load. It also casts floats to ints in an atomic load during AtomicExpand to support 128 bit vectors in SSE/AVX. commit-id:45989503
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4 files changed

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‎llvm/lib/Target/X86/X86ISelLowering.cpp

Copy file name to clipboardExpand all lines: llvm/lib/Target/X86/X86ISelLowering.cpp
+7Lines changed: 7 additions & 0 deletions
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@@ -32070,6 +32070,13 @@ X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
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}
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}
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TargetLowering::AtomicExpansionKind
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X86TargetLowering::shouldCastAtomicLoadInIR(LoadInst *LI) const {
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if (LI->getType()->getScalarType()->isFloatingPointTy())
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return AtomicExpansionKind::CastToInteger;
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return AtomicExpansionKind::None;
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}
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LoadInst *
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X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
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unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;

‎llvm/lib/Target/X86/X86ISelLowering.h

Copy file name to clipboardExpand all lines: llvm/lib/Target/X86/X86ISelLowering.h
+2Lines changed: 2 additions & 0 deletions
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@@ -1838,6 +1838,8 @@ namespace llvm {
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shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
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TargetLoweringBase::AtomicExpansionKind
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shouldExpandLogicAtomicRMWInIR(AtomicRMWInst *AI) const;
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TargetLoweringBase::AtomicExpansionKind
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shouldCastAtomicLoadInIR(LoadInst *LI) const override;
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void emitBitTestAtomicRMWIntrinsic(AtomicRMWInst *AI) const override;
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void emitCmpArithAtomicRMWIntrinsic(AtomicRMWInst *AI) const override;
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‎llvm/lib/Target/X86/X86InstrCompiler.td

Copy file name to clipboardExpand all lines: llvm/lib/Target/X86/X86InstrCompiler.td
+7Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1204,6 +1204,13 @@ def : Pat<(i16 (atomic_load_nonext_16 addr:$src)), (MOV16rm addr:$src)>;
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def : Pat<(i32 (atomic_load_nonext_32 addr:$src)), (MOV32rm addr:$src)>;
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def : Pat<(i64 (atomic_load_nonext_64 addr:$src)), (MOV64rm addr:$src)>;
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def : Pat<(v4i32 (scalar_to_vector (i32 (zext (i16 (atomic_load_16 addr:$src)))))),
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(MOVDI2PDIrm addr:$src)>; // load atomic <2 x i8>
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def : Pat<(v4i32 (scalar_to_vector (i32 (atomic_load_32 addr:$src)))),
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(MOVDI2PDIrm addr:$src)>; // load atomic <2 x i16>
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def : Pat<(v2i64 (scalar_to_vector (i64 (atomic_load_64 addr:$src)))),
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(MOV64toPQIrm addr:$src)>; // load atomic <2 x i32,float>
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// Floating point loads/stores.
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def : Pat<(atomic_store_32 (i32 (bitconvert (f32 FR32:$src))), addr:$dst),
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(MOVSSmr addr:$dst, FR32:$src)>, Requires<[UseSSE1]>;

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