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Commit 071898b

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rampitecrampitec
committed
[AMDGPU] Automate creation of byte_sel dags. NFCI.
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‎llvm/lib/Target/AMDGPU/SIInstrInfo.td

Copy file name to clipboardExpand all lines: llvm/lib/Target/AMDGPU/SIInstrInfo.td
+15-6Lines changed: 15 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1293,6 +1293,7 @@ def WaitVMVSrc : NamedIntOperand<"wait_vm_vsrc"> {
12931293
def ByteSel : NamedIntOperand<"byte_sel"> {
12941294
let Validator = "isUInt<2>";
12951295
}
1296+
def ByteSel0 : DefaultOperand<ByteSel, 0>;
12961297

12971298
let PrintMethod = "printBitOp3" in
12981299
def BitOp3 : NamedIntOperand<"bitop3">;
@@ -1971,7 +1972,8 @@ class getIns32 <RegisterOperand Src0RC, RegisterOperand Src1RC, int NumSrcArgs>
19711972
class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
19721973
RegisterOperand Src2RC, int NumSrcArgs,
19731974
bit HasClamp, bit HasModifiers, bit HasSrc2Mods, bit HasOMod,
1974-
Operand Src0Mod, Operand Src1Mod, Operand Src2Mod> {
1975+
Operand Src0Mod, Operand Src1Mod, Operand Src2Mod,
1976+
bit HasFP8ByteSel = 0, bit HasFP8DstByteSel = 0> {
19751977
dag src0 = !if(!ge(NumSrcArgs, 1),
19761978
!if (HasModifiers,
19771979
(ins Src0Mod:$src0_modifiers, Src0RC:$src0),
@@ -1989,18 +1991,23 @@ class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
19891991
(ins));
19901992
dag clamp = !if(HasClamp, (ins Clamp0:$clamp), (ins));
19911993
dag omod = !if(HasOMod, (ins omod0:$omod), (ins));
1994+
dag bytesel = !if(HasFP8ByteSel,
1995+
!con(!if(HasFP8DstByteSel, (ins VGPR_32:$vdst_in), (ins)),
1996+
(ins ByteSel0:$byte_sel)),
1997+
(ins));
19921998

1993-
dag ret = !con(src0, src1, src2, clamp, omod);
1999+
dag ret = !con(src0, src1, src2, clamp, omod, bytesel);
19942000
}
19952001

19962002
class getInsVOP3Base<RegisterOperand Src0RC, RegisterOperand Src1RC,
19972003
RegisterOperand Src2RC, int NumSrcArgs,
19982004
bit HasClamp, bit HasModifiers, bit HasSrc2Mods, bit HasOMod,
1999-
Operand Src0Mod, Operand Src1Mod, Operand Src2Mod, bit HasOpSel> {
2005+
Operand Src0Mod, Operand Src1Mod, Operand Src2Mod, bit HasOpSel,
2006+
bit HasFP8ByteSel = 0, bit HasFP8DstByteSel = 0> {
20002007
// getInst64 handles clamp and omod. implicit mutex between vop3p and omod
20012008
dag base = getIns64 <Src0RC, Src1RC, Src2RC, NumSrcArgs,
20022009
HasClamp, HasModifiers, HasSrc2Mods, HasOMod,
2003-
Src0Mod, Src1Mod, Src2Mod>.ret;
2010+
Src0Mod, Src1Mod, Src2Mod, HasFP8ByteSel, HasFP8DstByteSel>.ret;
20042011
dag opsel = (ins op_sel0:$op_sel);
20052012
dag ret = !con(base, !if(HasOpSel, opsel, (ins)));
20062013
}
@@ -2612,7 +2619,8 @@ class VOPProfile <list<ValueType> _ArgVT, bit _EnableClamp = 0> {
26122619
field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
26132620
field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
26142621
HasClamp, HasModifiers, HasSrc2Mods,
2615-
HasOMod, Src0Mod, Src1Mod, Src2Mod>.ret;
2622+
HasOMod, Src0Mod, Src1Mod, Src2Mod,
2623+
HasFP8ByteSel, HasFP8DstByteSel>.ret;
26162624
field dag InsVOP3P = getInsVOP3P<Src0RC64, Src1RC64, Src2RC64,
26172625
NumSrcArgs, HasClamp, HasOpSel, HasNeg,
26182626
Src0PackedMod, Src1PackedMod, Src2PackedMod>.ret;
@@ -2630,7 +2638,8 @@ class VOPProfile <list<ValueType> _ArgVT, bit _EnableClamp = 0> {
26302638
Src0ModDPP, Src1ModDPP, Src2ModDPP>.ret;
26312639
defvar InsVOP3DPPBase = getInsVOP3Base<Src0VOP3DPP, Src1VOP3DPP,
26322640
Src2VOP3DPP, NumSrcArgs, HasClamp, HasModifiers, HasSrc2Mods, HasOMod,
2633-
Src0ModVOP3DPP, Src1ModVOP3DPP, Src2ModVOP3DPP, HasOpSel>.ret;
2641+
Src0ModVOP3DPP, Src1ModVOP3DPP, Src2ModVOP3DPP, HasOpSel,
2642+
HasFP8ByteSel, HasFP8DstByteSel>.ret;
26342643
defvar InsVOP3PDPPBase = getInsVOP3P<Src0VOP3DPP, Src1VOP3DPP,
26352644
Src2VOP3DPP, NumSrcArgs, HasClamp, HasOpSel, HasNeg,
26362645
Src0ModVOP3DPP, Src1ModVOP3DPP, Src2ModVOP3DPP>.ret;

‎llvm/lib/Target/AMDGPU/VOP1Instructions.td

Copy file name to clipboardExpand all lines: llvm/lib/Target/AMDGPU/VOP1Instructions.td
-11Lines changed: 0 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -674,17 +674,6 @@ class VOPProfile_Base_CVT_F_F8_ByteSel<ValueType DstVT> : VOPProfile<[DstVT, i32
674674
let HasClamp = 0;
675675
let HasOMod = 0;
676676
let HasModifiers = 0;
677-
678-
defvar bytesel = (ins ByteSel:$byte_sel);
679-
let Ins64 = !con(getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
680-
HasClamp, HasModifiers, HasSrc2Mods,
681-
HasOMod, Src0Mod, Src1Mod, Src2Mod>.ret,
682-
bytesel);
683-
let InsVOP3Base = !con(getInsVOP3Base<Src0VOP3DPP, Src1VOP3DPP, Src2VOP3DPP,
684-
NumSrcArgs, HasClamp, HasModifiers, HasSrc2Mods,
685-
HasOMod, Src0ModVOP3DPP, Src1ModVOP3DPP,
686-
Src2ModVOP3DPP, HasOpSel>.ret,
687-
bytesel);
688677
}
689678

690679
let SubtargetPredicate = isGFX12Plus, OtherPredicates = [HasFP8ConversionInsts],

‎llvm/lib/Target/AMDGPU/VOP3Instructions.td

Copy file name to clipboardExpand all lines: llvm/lib/Target/AMDGPU/VOP3Instructions.td
+1-10Lines changed: 1 addition & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -593,6 +593,7 @@ def VOP3_CVT_SR_F8_F32_Profile : VOP3_Profile<VOPProfile<[i32, f32, i32, f32]>,
593593
let HasExtVOP3DPP = 1;
594594
let HasOpSel = 1;
595595
let HasFP8DstByteSel = 1;
596+
let HasFP8ByteSel = 0; // It works as a dst-bytesel, but does not have byte_sel operand.
596597
let AsmVOP3OpSel = !subst(", $src2_modifiers", "",
597598
getAsmVOP3OpSel<3, HasClamp, HasOMod,
598599
HasSrc0FloatMods, HasSrc1FloatMods,
@@ -607,16 +608,6 @@ class VOP3_CVT_SR_F8_ByteSel_Profile<ValueType SrcVT> :
607608
VOP3_Profile<VOPProfile<[i32, SrcVT, i32, untyped]>> {
608609
let HasFP8DstByteSel = 1;
609610
let HasClamp = 0;
610-
defvar bytesel = (ins VGPR_32:$vdst_in, ByteSel:$byte_sel);
611-
let Ins64 = !con(getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
612-
HasClamp, HasModifiers, HasSrc2Mods,
613-
HasOMod, Src0Mod, Src1Mod, Src2Mod>.ret,
614-
bytesel);
615-
let InsVOP3Base = !con(
616-
getInsVOP3Base<Src0VOP3DPP, Src1VOP3DPP,
617-
Src2VOP3DPP, NumSrcArgs, HasClamp, HasModifiers, HasSrc2Mods, HasOMod,
618-
Src0ModVOP3DPP, Src1ModVOP3DPP, Src2ModVOP3DPP, HasOpSel>.ret,
619-
bytesel);
620611
}
621612

622613
def IsPow2Plus1: PatLeaf<(i32 imm), [{

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