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Commit 0497911

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AZero13AZero13
committed
[SelectionDAG] Allow vselect in selection folds
It seems vselect was also meant to be an option given the comment and the fact vectors are allowed and the kind is checked too.
1 parent a23bd17 commit 0497911
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‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Copy file name to clipboardExpand all lines: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+10-6Lines changed: 10 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2490,7 +2490,8 @@ SDValue DAGCombiner::foldBinOpIntoSelect(SDNode *BO) {
24902490
unsigned SelOpNo = 0;
24912491
SDValue Sel = BO->getOperand(0);
24922492
auto BinOpcode = BO->getOpcode();
2493-
if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) {
2493+
if ((Sel.getOpcode() != ISD::SELECT && Sel.getOpcode() != ISD::VSELECT) ||
2494+
!Sel.hasOneUse()) {
24942495
SelOpNo = 1;
24952496
Sel = BO->getOperand(1);
24962497

@@ -2506,7 +2507,8 @@ SDValue DAGCombiner::foldBinOpIntoSelect(SDNode *BO) {
25062507
}
25072508
}
25082509

2509-
if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse())
2510+
if ((Sel.getOpcode() != ISD::SELECT && Sel.getOpcode() != ISD::VSELECT) ||
2511+
!Sel.hasOneUse())
25102512
return SDValue();
25112513

25122514
SDValue CT = Sel.getOperand(1);
@@ -10017,7 +10019,8 @@ SDValue DAGCombiner::visitShiftByConstant(SDNode *N) {
1001710019
BinOpLHSVal.getOpcode() == ISD::SRL) &&
1001810020
isa<ConstantSDNode>(BinOpLHSVal.getOperand(1));
1001910021
bool IsCopyOrSelect = BinOpLHSVal.getOpcode() == ISD::CopyFromReg ||
10020-
BinOpLHSVal.getOpcode() == ISD::SELECT;
10022+
BinOpLHSVal.getOpcode() == ISD::SELECT ||
10023+
BinOpLHSVal.getOpcode() == ISD::VSELECT;
1002110024

1002210025
if (!IsShiftByConstant && !IsCopyOrSelect)
1002310026
return SDValue();
@@ -13435,7 +13438,7 @@ static SDValue tryToFoldExtendOfConstant(SDNode *N, const SDLoc &DL,
1343513438
// fold (sext (select cond, c1, c2)) -> (select cond, sext c1, sext c2)
1343613439
// fold (zext (select cond, c1, c2)) -> (select cond, zext c1, zext c2)
1343713440
// fold (aext (select cond, c1, c2)) -> (select cond, sext c1, sext c2)
13438-
if (N0->getOpcode() == ISD::SELECT) {
13441+
if (N0->getOpcode() == ISD::SELECT || N0->getOpcode() == ISD::VSELECT) {
1343913442
SDValue Op1 = N0->getOperand(1);
1344013443
SDValue Op2 = N0->getOperand(2);
1344113444
if (isa<ConstantSDNode>(Op1) && isa<ConstantSDNode>(Op2) &&
@@ -17763,10 +17766,11 @@ SDValue DAGCombiner::visitFMUL(SDNode *N) {
1776317766
// fold (fmul X, (select (fcmp X > 0.0), -1.0, 1.0)) -> (fneg (fabs X))
1776417767
// fold (fmul X, (select (fcmp X > 0.0), 1.0, -1.0)) -> (fabs X)
1776517768
if (Flags.hasNoNaNs() && Flags.hasNoSignedZeros() &&
17766-
(N0.getOpcode() == ISD::SELECT || N1.getOpcode() == ISD::SELECT) &&
17769+
(N0.getOpcode() == ISD::SELECT || N0.getOpcode() == ISD::VSELECT ||
17770+
N1.getOpcode() == ISD::SELECT || N1.getOpcode() == ISD::VSELECT) &&
1776717771
TLI.isOperationLegal(ISD::FABS, VT)) {
1776817772
SDValue Select = N0, X = N1;
17769-
if (Select.getOpcode() != ISD::SELECT)
17773+
if (Select.getOpcode() != ISD::SELECT && Select.getOpcode() != ISD::VSELECT)
1777017774
std::swap(Select, X);
1777117775

1777217776
SDValue Cond = Select.getOperand(0);

‎llvm/test/CodeGen/RISCV/rvv/narrow-shift-extend.ll

Copy file name to clipboardExpand all lines: llvm/test/CodeGen/RISCV/rvv/narrow-shift-extend.ll
+1-2Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -144,8 +144,7 @@ define <vscale x 4 x i32> @test_vloxei7(ptr %ptr, <vscale x 4 x i1> %offset, i64
144144
; CHECK: # %bb.0: # %entry
145145
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma
146146
; CHECK-NEXT: vmv.v.i v8, 0
147-
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
148-
; CHECK-NEXT: vsll.vi v12, v8, 2
147+
; CHECK-NEXT: vmerge.vim v12, v8, 4, v0
149148
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
150149
; CHECK-NEXT: vloxei64.v v8, (a0), v12
151150
; CHECK-NEXT: ret

‎llvm/test/CodeGen/X86/extract-vselect-setcc.ll

Copy file name to clipboardExpand all lines: llvm/test/CodeGen/X86/extract-vselect-setcc.ll
+5-5Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -5,11 +5,11 @@ define void @PR117684(i1 %cond, <8 x float> %vec, ptr %ptr1, ptr %ptr2) #0 {
55
; CHECK-LABEL: PR117684:
66
; CHECK: # %bb.0:
77
; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
8-
; CHECK-NEXT: vcmpnltss %xmm1, %xmm0, %k1
9-
; CHECK-NEXT: vbroadcastss {{.*#+}} xmm0 = [NaN,NaN,NaN,NaN]
10-
; CHECK-NEXT: vinsertf32x4 $0, %xmm0, %ymm0, %ymm0 {%k1} {z}
11-
; CHECK-NEXT: vmulss %xmm1, %xmm0, %xmm0
12-
; CHECK-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
8+
; CHECK-NEXT: vmovss {{.*#+}} xmm2 = [NaN,0.0E+0,0.0E+0,0.0E+0]
9+
; CHECK-NEXT: vcmpltss %xmm1, %xmm0, %k1
10+
; CHECK-NEXT: vmovaps %xmm2, %xmm0
11+
; CHECK-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1}
12+
; CHECK-NEXT: vmulss %xmm2, %xmm0, %xmm2
1313
; CHECK-NEXT: vbroadcastss %xmm2, %ymm2
1414
; CHECK-NEXT: testb $1, %dil
1515
; CHECK-NEXT: cmoveq %rdx, %rsi

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