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Commit 03677f6

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lucas-ramilucas-rami
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[MachineScheduler] Optional scheduling of single-MI regions (#129704)
Following 15e295d the machine scheduler no longer filters-out single-MI regions when emitting regions to schedule. While this has no functional impact at the moment, it generally has a negative compile-time impact (see #128739). Since all targets but AMDGPU do not care for this behavior, this introduces an off-by-default flag to `ScheduleDAGInstrs` to control whether such regions are going to be scheduled, effectively reverting 15e295d for all targets but AMDGPU (currently the only target enabling this flag).
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‎llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h

Copy file name to clipboardExpand all lines: llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
+8Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -124,6 +124,9 @@ namespace llvm {
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/// rescheduling).
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bool RemoveKillFlags;
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/// True if regions with a single MI should be scheduled.
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bool ScheduleSingleMIRegions = false;
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/// The standard DAG builder does not normally include terminators as DAG
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/// nodes because it does not create the necessary dependencies to prevent
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/// reordering. A specialized scheduler can override
@@ -288,6 +291,11 @@ namespace llvm {
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return Topo.IsReachable(SU, TargetSU);
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}
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/// Whether regions with a single MI should be scheduled.
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bool shouldScheduleSingleMIRegions() const {
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return ScheduleSingleMIRegions;
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}
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/// Returns an iterator to the top of the current scheduling region.
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MachineBasicBlock::iterator begin() const { return RegionBegin; }
293301

‎llvm/lib/CodeGen/MachineScheduler.cpp

Copy file name to clipboardExpand all lines: llvm/lib/CodeGen/MachineScheduler.cpp
+4-5Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -769,6 +769,7 @@ void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler,
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MBBRegionsVector MBBRegions;
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getSchedRegions(&*MBB, MBBRegions, Scheduler.doMBBSchedRegionsTopDown());
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bool ScheduleSingleMI = Scheduler.shouldScheduleSingleMIRegions();
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for (const SchedRegion &R : MBBRegions) {
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MachineBasicBlock::iterator I = R.RegionBegin;
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MachineBasicBlock::iterator RegionEnd = R.RegionEnd;
@@ -778,11 +779,9 @@ void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler,
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// it. Perhaps it still needs to be bundled.
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Scheduler.enterRegion(&*MBB, I, RegionEnd, NumRegionInstrs);
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// Skip empty scheduling regions but include single-MI regions; we want
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// those to be scheduled so that backends which move MIs across regions
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// during scheduling can reason about and schedule those regions
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// correctly.
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if (I == RegionEnd) {
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// Skip empty scheduling regions and, conditionally, regions with a single
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// MI.
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if (I == RegionEnd || (!ScheduleSingleMI && I == std::prev(RegionEnd))) {
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// Close the current region. Bundle the terminator if needed.
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// This invalidates 'RegionEnd' and 'I'.
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Scheduler.exitRegion();

‎llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp

Copy file name to clipboardExpand all lines: llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+4Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -760,6 +760,10 @@ GCNScheduleDAGMILive::GCNScheduleDAGMILive(
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StartingOccupancy(MFI.getOccupancy()), MinOccupancy(StartingOccupancy),
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RegionLiveOuts(this, /*IsLiveOut=*/true) {
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// We want regions with a single MI to be scheduled so that we can reason
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// about them correctly during scheduling stages that move MIs between regions
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// (e.g., rematerialization).
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ScheduleSingleMIRegions = true;
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LLVM_DEBUG(dbgs() << "Starting occupancy is " << StartingOccupancy << ".\n");
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if (RelaxedOcc) {
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MinOccupancy = std::min(MFI.getMinAllowedOccupancy(), StartingOccupancy);

‎llvm/test/CodeGen/ARM/misched-branch-targets.mir

Copy file name to clipboardExpand all lines: llvm/test/CodeGen/ARM/misched-branch-targets.mir
+5-6Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
1-
# RUN: llc -o - -run-pass=machine-scheduler -misched=shuffle %s | FileCheck -check-prefixes=CHECK,CHECK-MISCHED %s
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# RUN: llc -o - -passes=machine-scheduler -misched=shuffle %s | FileCheck -check-prefixes=CHECK,CHECK-MISCHED %s
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# RUN: llc -o - -run-pass=postmisched %s | FileCheck -check-prefixes=CHECK,CHECK-POSTMISCHED %s
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# RUN: llc -o - -passes=postmisched %s | FileCheck -check-prefixes=CHECK,CHECK-POSTMISCHED %s
1+
# RUN: llc -o - -run-pass=machine-scheduler -misched=shuffle %s | FileCheck %s
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# RUN: llc -o - -passes=machine-scheduler -misched=shuffle %s | FileCheck %s
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# RUN: llc -o - -run-pass=postmisched %s | FileCheck %s
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# RUN: llc -o - -passes=postmisched %s | FileCheck %s
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# REQUIRES: asserts
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# -misched=shuffle is only available with assertions enabled
@@ -147,8 +147,7 @@ body: |
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# CHECK-LABEL: name: foo_setjmp
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# CHECK: body:
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# CHECK-MISCHED: tBL 14 /* CC::al */, $noreg, @setjmp, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit-def $sp, implicit-def $r0
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# CHECK-POSTMISCHED: tBL 14 /* CC::al */, $noreg, @setjmp, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0
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# CHECK: tBL 14 /* CC::al */, $noreg, @setjmp, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0
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# CHECK-NEXT: t2BTI
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---

‎llvm/test/CodeGen/X86/fake-use-scheduler.mir

Copy file name to clipboardExpand all lines: llvm/test/CodeGen/X86/fake-use-scheduler.mir
-6Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -9,12 +9,6 @@
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#
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# CHECK: ********** MI Scheduling **********
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# CHECK-NEXT: foo:%bb.0 entry
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# CHECK-NEXT: From: $rax = COPY %5:gr64
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# CHECK-NEXT: To: RET 0, killed $rax
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# CHECK-NEXT: RegionInstrs: 1
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#
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# CHECK: ********** MI Scheduling **********
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# CHECK-NEXT: foo:%bb.0 entry
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# CHECK-NEXT: From: %0:gr64 = COPY $rdi
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# CHECK-NEXT: To: FAKE_USE %5:gr64
2014
# CHECK-NEXT: RegionInstrs: 7

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