This CPU implementation uses the RISC-V ISA, version RV32I. It is a 32-bit architecture and implements the following subset of RV32I instructions:
add, addi, and, sub, slli, srai, srli, slt
bne, beq, , jal, jalr
lw, sw, lui
mv, nop, j, jr, la, ret
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konicst1/RISC-V-single-cycle-processor
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Verilog implementation of RISC-V 32bit single cycle processor
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