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Commit 8709336

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Raienryu97me-no-dev
Raienryu97
authored and
me-no-dev
committed
ResetReason: Add an additional method and a test case (espressif#467)
Method: -------- Added a verbose print method for ease. Test Case: ----------- Putting ESP32 to sleep will give a different reason on wake than the first time power up.
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‎libraries/ESP32/examples/ResetReason/ResetReason.ino

Copy file name to clipboardExpand all lines: libraries/ESP32/examples/ResetReason/ResetReason.ino
+105-5Lines changed: 105 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,21 @@
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/* Print last reset reason of ESP32
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* by Evandro Luis Copercini - 2017
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/*
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* Print last reset reason of ESP32
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* =================================
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*
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* Use either of the methods print_reset_reason
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* or verbose_print_reset_reason to display the
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* cause for the last reset of this device.
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*
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* Public Domain License.
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*
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* Author:
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* Evandro Luis Copercini - 2017
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*/
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#include <rom/rtc.h>
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#define uS_TO_S_FACTOR 1000000 /* Conversion factor for micro seconds to seconds */
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void print_reset_reason(RESET_REASON reason)
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{
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switch ( reason)
@@ -28,20 +39,109 @@ void print_reset_reason(RESET_REASON reason)
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}
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}
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void verbose_print_reset_reason(RESET_REASON reason)
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{
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switch ( reason)
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{
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case 1 : Serial.println ("Vbat power on reset");break;
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case 3 : Serial.println ("Software reset digital core");break;
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case 4 : Serial.println ("Legacy watch dog reset digital core");break;
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case 5 : Serial.println ("Deep Sleep reset digital core");break;
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case 6 : Serial.println ("Reset by SLC module, reset digital core");break;
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case 7 : Serial.println ("Timer Group0 Watch dog reset digital core");break;
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case 8 : Serial.println ("Timer Group1 Watch dog reset digital core");break;
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case 9 : Serial.println ("RTC Watch dog Reset digital core");break;
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case 10 : Serial.println ("Instrusion tested to reset CPU");break;
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case 11 : Serial.println ("Time Group reset CPU");break;
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case 12 : Serial.println ("Software reset CPU");break;
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case 13 : Serial.println ("RTC Watch dog Reset CPU");break;
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case 14 : Serial.println ("for APP CPU, reseted by PRO CPU");break;
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case 15 : Serial.println ("Reset when the vdd voltage is not stable");break;
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case 16 : Serial.println ("RTC Watch dog reset digital core and rtc module");break;
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default : Serial.println ("NO_MEAN");
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}
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}
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void setup() {
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// put your setup code here, to run once:
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Serial.begin(115200);
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delay(2000);
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Serial.println("CPU0 reset reason: ");
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Serial.println("CPU0 reset reason:");
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print_reset_reason(rtc_get_reset_reason(0));
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verbose_print_reset_reason(rtc_get_reset_reason(0));
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Serial.println("CPU1 reset reason: ");
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Serial.println("CPU1 reset reason:");
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print_reset_reason(rtc_get_reset_reason(1));
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verbose_print_reset_reason(rtc_get_reset_reason(1));
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// Set ESP32 to go to deep sleep to see a variation
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// in the reset reason. Device will sleep for 5 seconds.
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esp_deep_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_OFF);
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Serial.println("Going to sleep");
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esp_deep_sleep(5 * uS_TO_S_FACTOR);
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}
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void loop() {
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// put your main code here, to run repeatedly:
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}
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}
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/*
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Example Serial Log:
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====================
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rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
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configsip: 0, SPIWP:0x00
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clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
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mode:DIO, clock div:1
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load:0x3fff0008,len:8
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load:0x3fff0010,len:160
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load:0x40078000,len:10632
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load:0x40080000,len:252
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entry 0x40080034
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CPU0 reset reason:
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RTCWDT_RTC_RESET
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RTC Watch dog reset digital core and rtc module
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CPU1 reset reason:
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EXT_CPU_RESET
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for APP CPU, reseted by PRO CPU
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Going to sleep
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ets Jun 8 2016 00:22:57
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rst:0x5 (DEEPSLEEP_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
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configsip: 0, SPIWP:0x00
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clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
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mode:DIO, clock div:1
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load:0x3fff0008,len:8
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load:0x3fff0010,len:160
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load:0x40078000,len:10632
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load:0x40080000,len:252
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entry 0x40080034
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CPU0 reset reason:
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DEEPSLEEP_RESET
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Deep Sleep reset digital core
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CPU1 reset reason:
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EXT_CPU_RESET
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for APP CPU, reseted by PRO CPU
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Going to sleep
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ets Jun 8 2016 00:22:57
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rst:0x5 (DEEPSLEEP_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
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configsip: 0, SPIWP:0x00
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clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
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mode:DIO, clock div:1
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load:0x3fff0008,len:8
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load:0x3fff0010,len:160
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load:0x40078000,len:10632
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load:0x40080000,len:252
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entry 0x40080034
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CPU0 reset reason:
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DEEPSLEEP_RESET
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Deep Sleep reset digital core
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CPU1 reset reason:
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EXT_CPU_RESET
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for APP CPU, reseted by PRO CPU
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Going to sleep
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*/

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