igzip/riscv64: Add adler32_rvv optimization for VLEN=128 #374
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@sunyuechi can you review this? Thanks! |
| addi sp, sp, -32 | ||
| sd ra, 24(sp) | ||
| sd s1, 16(sp) | ||
| sd s2, 8(sp) |
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You can use the unused registers to reduce stack operations (at least a7, t5)
| slli s1, a0, 48 | ||
| srli s1, s1, 48 // s1: A = adler32 & 0xffff | ||
| srliw s2, a0, 16 // s2: B = adler32 >> 16 | ||
| add s3, a1, a2 // s3 = end |
| la a7, factors | ||
| vle8.v v0, (a7) | ||
| vmv.v.i v4, 0 | ||
| vmv.v.i v8, 0 |
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v4 hasn’t been modified, so you can just use v4.
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Done, thanks for the review!
| mv t2, t1 | ||
| 1: | ||
| mv a3, t5 | ||
| mv a4, t6 |
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t5, t6 -> a3, a4
update a3, a4
a3, a4 -> t5, t6
It doesn’t seem to be needed here — is it fine to just update t5 and t6 directly?
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Done, thanks for the review!
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| mul a3, t6, t3 | ||
| srli a3, a3, 47 | ||
| mul a4, a3, t4 | ||
| sub t6, t6, a4 |
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You can directly copy the same 8 lines with the logic above. Not changing the temporary registers makes it a bit clearer. Then combine these commits into one, and it should be ready to be merged.
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Done, thanks for the review!
Signed-off-by: WenLei <lei.wen2@zte.com.cn>
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@sunyuechi is this OK to merge now? |
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@pablodelara ok |
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Could this PR be merged, or is there anything else I need to change? Thanks! |
This PR introduces an optimized adler32_rvv implementation for vlen=128.
The optimization has been verified on the SG2044 platform: