hydevcode
diff --git a/‎.github/workflows/bsp_buildings.yml
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diff --git a/‎bsp/wch/risc-v/Libraries/Kconfig
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diff --git a/‎bsp/wch/risc-v/Libraries/ch32v20x_libraries/.ignore_format.yml
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diff --git a/‎bsp/wch/risc-v/Libraries/ch32v20x_libraries/SConscript
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diff --git a/‎bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/SConscript
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diff --git a/‎bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/include/ch32v20x_conf.h
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diff --git a/‎bsp/wch/risc-v/Libraries/ch32v20x_libraries/bmsis/include/ch32v20x_it.h
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@@ -354,6 +354,7 @@ jobs:
             RTT_TOOL_CHAIN: "sourcery-riscv-none-embed"
             SUB_RTT_BSP:  
                 - "k210"
+                - "wch/risc-v/ch32v208w-r0"
                 - "wch/risc-v/ch32v307v-r1"
                 - "wch/risc-v/yd-ch32v307vct6"
          -  RTT_BSP: "riscv64-unknown" 
 
@@ -12,6 +12,16 @@ config SOC_RISCV_SERIES_CH32V2
     select ARCH_RISCV
     select SOC_RISCV_FAMILY_CH32
     select RT_USING_HW_ATOMIC
+    select PKG_USING_CH32V20x_SDK
+
+config SOC_RISCV_SERIES_CH32V20x_D6
+    bool
+
+config SOC_RISCV_SERIES_CH32V20x_D8
+    bool
+
+config SOC_RISCV_SERIES_CH32V20x_D8W
+    bool
 
 config SOC_RISCV_SERIES_CH32V3
     bool