Hi all,

I've noticed that most of the HDL modules do not include explicit reset signals. As far as I understand, this follows AMD/Xilinx’s design philosophy to avoid resets where possible and rely on default initialization instead.

However, in our environment this leads to practical issues. Specifically, we have systems where the clock is delivered externally via fiber. If the fiber connection is temporarily removed and reconnected, the clock stops and restarts. After the clock becomes stable again, the design must be properly reset — otherwise, modules may remain in an undefined state.

This is particularly problematic with FIFOs and other stateful components. Without an explicit reset, they may behave unpredictably after clock recovery, and require several cycles to flush or resynchronize before normal operation can resume.

Are there any plans to support optional reset signals, for example, via optional interface ports, to ensure clean reinitialization in such scenarios?

Best,
Maxi