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Commit c688f30

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fix(clk_src): Fix error as APLL is not yet supported for P4
1 parent 1ef1e7d commit c688f30
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‎cores/esp32/esp32-hal-cpu.c

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+2-11Lines changed: 2 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -259,18 +259,10 @@ bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz) {
259259
if (apb_change_callbacks) {
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triggerApbChangeCallback(APB_AFTER_CHANGE, capb, apb);
261261
}
262-
// clang-format off
263-
#ifdef SOC_CLK_APLL_SUPPORTED
262+
#if defined(SOC_CLK_APLL_SUPPORTED) && !defined(CONFIG_IDF_TARGET_ESP32P4) // APLL not yet supported in ESP32-P4
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log_d(
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"%s: %u / %u = %u Mhz, APB: %u Hz",
266-
(conf.source == SOC_CPU_CLK_SRC_PLL) ? "PLL"
267-
: ((conf.source == SOC_CPU_CLK_SRC_APLL) ? "APLL"
268-
: ((conf.source == SOC_CPU_CLK_SRC_XTAL) ? "XTAL"
269-
#ifdef CONFIG_IDF_TARGET_ESP32P4
270-
: "17.5M")),
271-
#else
272-
: "8M")),
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#endif
265+
(conf.source == SOC_CPU_CLK_SRC_PLL) ? "PLL" : ((conf.source == SOC_CPU_CLK_SRC_APLL) ? "APLL" : ((conf.source == SOC_CPU_CLK_SRC_XTAL) ? "XTAL" : "8M")),
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conf.source_freq_mhz, conf.div, conf.freq_mhz, apb
275267
);
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#else
@@ -279,7 +271,6 @@ bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz) {
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conf.source_freq_mhz, conf.div, conf.freq_mhz, apb
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);
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#endif
282-
// clang-format on
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return true;
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}
285276

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