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gagana-05/README.md
  • 👋 Hi, I’m @gagana-05
  • 👀 I’m interested in Digital System Design, Computer Architecture, Embedded Systems
  • 🌱 I’m currently learning RTL Design, FPGAs, VLSI
  • 💞️ I’m looking to collaborate on hardware digital projects pertaining to my domain
  • 📫 How to reach me LinkedIn

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  1. IEEE-NITK/VLSI_design-of-RISC IEEE-NITK/VLSI_design-of-RISC Public

    IEEE Executive project for the year 2021-2022

    Verilog 11 2

  2. RISC-V-CPU-Core RISC-V-CPU-Core Public

    This repo contains the codes which I implemented while completing the course "Building a RISC-V CPU Core" offered by Linux Foundation through edx.

    1

  3. Term-Project Term-Project Public

    Verilog

  4. caravel_cocotb caravel_cocotb Public

    Verilog

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