4848constexpr int32_t MAXIRQTICKSCCYS = microsecondsToClockCycles(10000 );
4949// Maximum servicing time for any single IRQ
5050constexpr uint32_t ISRTIMEOUTCCYS = microsecondsToClockCycles(18 );
51- // The SDK and hardware take some time to actually get to our NMI code, so
52- // decrement the next IRQ's timer value by a bit so we can actually catch the
53- // real CPU cycle count we want for the waveforms.
54- constexpr int32_t DELTAIRQCCYS = clockCyclesPerMicrosecond() == 160 ?
55- microsecondsToClockCycles (1 ) >> 1 : microsecondsToClockCycles(1 );
5651// The latency between in-ISR rearming of the timer and the earliest firing
5752constexpr int32_t IRQLATENCYCCYS = clockCyclesPerMicrosecond() == 160 ?
5853 microsecondsToClockCycles (1 ) >> 1 : microsecondsToClockCycles(1 );
@@ -187,7 +182,7 @@ int startWaveformClockCycles(uint8_t pin, uint32_t highCcys, uint32_t lowCcys,
187182 if (!waveform.timer1Running ) {
188183 initTimer ();
189184 }
190- else if (T1V > ((clockCyclesPerMicrosecond () == 160 ) ? ( IRQLATENCYCCYS + DELTAIRQCCYS) >> 1 : IRQLATENCYCCYS + DELTAIRQCCYS )) {
185+ else if (T1V > ((clockCyclesPerMicrosecond () == 160 ) ? IRQLATENCYCCYS >> 1 : IRQLATENCYCCYS)) {
191186 // Must not interfere if Timer is due shortly
192187 timer1_write (IRQLATENCYCCYS);
193188 }
@@ -224,7 +219,7 @@ int ICACHE_RAM_ATTR stopWaveform(uint8_t pin) {
224219 waveform.toDisableBits = 1UL << pin;
225220 std::atomic_thread_fence (std::memory_order_release);
226221 // Must not interfere if Timer is due shortly
227- if (T1V > ((clockCyclesPerMicrosecond () == 160 ) ? ( IRQLATENCYCCYS + DELTAIRQCCYS) >> 1 : IRQLATENCYCCYS + DELTAIRQCCYS )) {
222+ if (T1V > ((clockCyclesPerMicrosecond () == 160 ) ? IRQLATENCYCCYS >> 1 : IRQLATENCYCCYS)) {
228223 timer1_write (IRQLATENCYCCYS);
229224 }
230225 while (waveform.toDisableBits ) {
@@ -306,7 +301,7 @@ static ICACHE_RAM_ATTR void timer1Interrupt() {
306301 uint32_t now = ESP.getCycleCount ();
307302 uint32_t isrNextEventCcy = now;
308303 while (busyPins) {
309- if (static_cast <int32_t >(isrNextEventCcy - now) > IRQLATENCYCCYS + DELTAIRQCCYS ) {
304+ if (static_cast <int32_t >(isrNextEventCcy - now) > IRQLATENCYCCYS) {
310305 waveform.nextEventCcy = isrNextEventCcy;
311306 break ;
312307 }
@@ -412,15 +407,9 @@ static ICACHE_RAM_ATTR void timer1Interrupt() {
412407 }
413408
414409 // Firing timer too soon, the NMI occurs before ISR has returned.
415- if (nextTimerCcys <= IRQLATENCYCCYS + DELTAIRQCCYS ) {
410+ if (nextTimerCcys <= IRQLATENCYCCYS) {
416411 nextTimerCcys = IRQLATENCYCCYS;
417412 }
418- else if (nextTimerCcys >= MAXIRQTICKSCCYS + DELTAIRQCCYS) {
419- nextTimerCcys = MAXIRQTICKSCCYS;
420- }
421- else {
422- nextTimerCcys -= DELTAIRQCCYS;
423- }
424413
425414 // Register access is fast and edge IRQ was configured before.
426415 // Timer is 80MHz fixed. 160MHz binaries need scaling.
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