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variable_drivers_group and variable_loads_group reject my loads() and drivers() assignment.

Status: Open.

#1102 In chipsalliance/UHDM;

· mlr11 opened on Apr 27, 2025

VPI: Unable to get driver/load

Status: Open.

#1101 In chipsalliance/UHDM;

· heyfey opened on Apr 10, 2025

Obtaining module handle based on the full name of the instance

Status: Open.

#1080 In chipsalliance/UHDM;

· mysoreanoop opened on Jun 28, 2024

Efficient backtracking from output ports to input ports

Status: Open.

#1078 In chipsalliance/UHDM;

· alaindargelas opened on Jun 25, 2024

Create a RTL Netlist view

Status: Open.

#1037 In chipsalliance/UHDM;

· alaindargelas opened on Oct 5, 2023

[feature suggestion] Save/restore UHDM in-memory

Status: Open.

#902 In chipsalliance/UHDM;

· yurivict opened on Apr 2, 2023

Create "standalone" examples

Status: Open.

#783 In chipsalliance/UHDM;

· alaindargelas opened on Aug 23, 2022

Consider publishing generated capnp and uhdm_types.h as release artifacts

Status: Open.

#498 In chipsalliance/UHDM;

· MikePopoloski opened on Sep 13, 2021

Support a second parser (other than Surelog)

enhancementNew feature or requestNew feature or request

Status: Open.

#319 In chipsalliance/UHDM;

· mithro opened on Jul 24, 2020

Generate a class hierarchy diagram for generated models

Status: Open.

#207 In chipsalliance/UHDM;

· hs-apotell opened on May 7, 2020

Create SystemVerilog Constraints Model

Status: Open.

#185 In chipsalliance/UHDM;

· alaindargelas opened on Apr 22, 2020

Set up Kokoro CI on this repository

Status: Open.

#178 In chipsalliance/UHDM;

· mithro opened on Apr 15, 2020