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1. HelloWorld HelloWorld Public

   Sanity Check

2. cve2 cve2 Public

   Forked from openhwgroup/cve2

   The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC. Local changes to adapt t…

   SystemVerilog

3. axi axi Public

   Forked from pulp-platform/axi

   AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

   SystemVerilog

4. rv_plic rv_plic Public

   Forked from pulp-platform/rv_plic

   Development Fork (unstable)

   SystemVerilog

5. register_interface register_interface Public

   Forked from pulp-platform/register_interface

   Generic Register Interface (contains various adapters)

   SystemVerilog

6. riscv-dbg riscv-dbg Public

   Forked from pulp-platform/riscv-dbg

   RISC-V Debug Support for our PULP RISC-V Cores

   SystemVerilog