A tool to convert PRS into Verilog for accelerated simulation on FPGA
Original Paper
Run:

prs2fpga -h

to see usage menu.

If you use this tool for a publication, please reference the following paper (linked above):

• Ruslan Dashkin and Rajit Manohar. General Approach to Asynchronous Circuits Simulation Using Synchronous FPGAs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems doi: 10.1109/TCAD.2021.3131546.