@@ -5,7 +5,7 @@ void clockout(uint32_t gclk, int32_t divisor)
55 GCLK_GENDIV_Type gendiv =
66 {
77 .bit .DIV = divisor , // divider, linear or 2^(.DIV+1)
8- .bit .ID = gclk , // GCLK_GENERATOR_X
8+ .bit .ID = gclk , // GCLK_GENERATOR_"gclk"
99 };
1010 GCLK -> GENDIV .reg = gendiv .reg ;
1111
@@ -14,15 +14,17 @@ void clockout(uint32_t gclk, int32_t divisor)
1414 {
1515 .bit .RUNSTDBY = 0 , // Run in Standby
1616 .bit .DIVSEL = 0 , // .DIV (above) Selection: 0=linear 1=powers of 2
17- .bit .OE = 1 , // Output Enable to observe on a port pin
17+ .bit .OE = 1 , // Output Enable to observe on any port pin capable of outputting GCLK_IO["gclk"]
1818 .bit .OOV = 0 , // Output Off Value
1919 .bit .IDC = 1 , // Improve Duty Cycle
2020 .bit .GENEN = 1 , // enable this GCLK
21- // select GCLK source
2221 //.bit.SRC = GCLK_SOURCE_OSC8M,
23- .bit .SRC = GCLK_SOURCE_DFLL48M ,
24- // select GCLK2 to output on
25- .bit .ID = gclk , // GCLK_GENERATOR_X
22+ .bit .SRC = GCLK_SOURCE_DFLL48M , // select GCLK source
23+ .bit .ID = gclk , // output GCLK_GENERATOR_"gclk" on GCLK_IO["gclk"]
2624 };
2725 GCLK -> GENCTRL .reg = genctrl .reg ;
28- }
26+ while ( GCLK -> STATUS .reg & GCLK_STATUS_SYNCBUSY )
27+ {
28+ /* Wait for synchronization */
29+ }
30+ }
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