Prototype for using a reactive dependency graph as the execution model of a hardware emulator. Two primitives, Signal (mutable value) and Derived (cached computation), form a dependency graph that tracks what depends on what and only recomputes what's actually stale. Bus maps signals to an address space, Scheduler handles things that need to happen at specific cycles.

Hardware is reactive dataflow. Signals propagate through combinational logic, registers latch on clock edges. The emulator mirrors that structure instead of imposing a tick-everything loop. The graph gets you lazy evaluation, dirty tracking, backdating (same-value writes are absorbed), and dependency narrowing (branches not taken don't create edges).

This is a Python prototype. The ideas hold up and the performance ratios are what you'd expect, but it's Python. Substrate is a Zig library built from the same research, implementing the core incremental computation primitives (Cell, Memo, four cancellation layers) with flat arrays and SoA layout. It's a work in progress.

Python 3.10+, no dependencies.

python demo.py             # toy 8×8 PPU: dependency tracking, backdating, gating
python bench.py            # reactive vs naive recompute across workload patterns
python timer_demo.py       # cross-component coupling (DIV/timer/APU)
python raster_demo.py      # mid-scanline register writes via push-pull scheduling
python introspection_demo.py  # causal debugging, impact analysis, counterfactuals
python rewind_demo.py      # state snapshots, diffs, deterministic rewind

Every *_demo.py is self-contained and runnable. 27 total, each testing a different part of the architecture. A few worth looking at beyond the ones above: temporal (closed-form state with reactive deopt), jit (stability profiling and block caching), adversarial (worst cases), integrated (all subsystems running together). Each file has a docstring explaining what it's doing and why.

reactive.py (~370 lines). Signal, Derived, Bus, Scheduler. Everything else imports from it.

ISC