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Verilator testbench for ISA tests #8
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Changed FPGA build makefile to use e203 as a default CORE and did few minor enhancements. Updated SDK makefile to let users re-define toolchain binaries names from environment. This shall help using different pre-compiled toolchains.
Testbench and Makefile added into a separate folder (originating from the existing ISA tests testbench). Minor updates to Verilog code to let it work with Verilator. Run with v3.924 and --trace enabled (without --trace the simulation does not converge/end).
Also added help target to the Makefile so that it becomes the default one. Added README file with instructions and known limitations. Added license statements (Apache 2.0).
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This pull requests adds a testbench and Makefile to run ISA tests against RTL with Verilator.
There are minor changes in RTL to make it work with Verilator. Minor changes also made in fpga and SDK Makefiles (these are not needed for the Verilator testbech).