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This repository was archived by the owner on Mar 24, 2021. It is now read-only.

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xxqfhj
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@xxqfhj xxqfhj commented Jul 14, 2019

There is combination loop in icb_claim_irq and icb_complete_irq assign logic.
This loop will make the simulation tool time stuck(the tool is ncsim), and
lint/synthesize can't found this loop. After analysis, I think lint tool treat
the logic "a=0; a=a|b;" same as "a=b;" in function, so lint and synthesize
tool don't report this loop because it optimize this logic.
After change this logic to "a=b;" directly, simulation could runs to final.

Signed-off-by: xxqfhj xxqfhj@github.com

There is combination loop in icb_claim_irq and icb_complete_irq assign logic.
This loop will make the simulation tool time stuck(the tool is ncsim), and
lint/synthesize can't found this loop. After analysis, I think lint tool treat
the logic "a=0; a=a|b;" same as "a=b;" in function, so lint and synthesize
tool don't report this loop because it optimize this logic.
After change this logic to "a=b;" directly, simulation could runs to final.

Signed-off-by: xxqfhj <xxqfhj@github.com>
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