This is a tool which generates AXI4-Lite slave from a description in SystemRDL.

It uses systemrdl-compiler as a front end and a custom backend to generate a VHDL module.

The HECTARE tool is developed by MicroTCA Tech Lab at DESY.

$ hectare.py --help
usage: hectare.py [-h] [--debug] [--axi-vhdl VHDL_NAME] filename

HECTARE - Hamburg Elegant CreaTor from Accelera systemrdl to REgisters

positional arguments:
  filename              .rdl file

optional arguments:
  -h, --help            show this help message and exit
  --debug               enable debugging information
  --axi-vhdl VHDL_NAME  generate AXI4-Lite slave

• sw: r, rw, w, na
• hw: r, rw, w, na
• swmod
• singlepulse
• woclr
• encode

• Read decode error returns 0xbadcofee

• Add support for woclr

• Add support for singlepulse

• Add C header generator
• Add support for reset values
• Add version argument (--version) to print version information

• First public release
• Provides generation of AXI4-Lite module in VHDL
• Supports all possible combination for sw and rw properties as well as swmod and encode attribute

Several tests are provided in test folder

This is a simple unit test based on the Python [] framework.

UVVM version: v2019.12.04

Regenerating the output products (in shell, from folder hdl):

$ ./gen_output.sh
Parsing finished.
generate_package
Generating mymodule.vhd ...
Generating mymodule_pkg.vhd ...
Done.

Running the test (in ModelSim, from folder work)

do ../scripts/compile_uvvm.do
do ../scripts/sim.do

Requires hdlparse from a fork (the one from pip is missing some features) available from https://github.com/andresmanelli/hdlparse on branch entity.

Compares the output of HECTARE against Juniper® ordt.

Alias to ordt should be created, as explained here.

Accellera™ and SystemRDL™ are trademarks of Accellera Systems Initiative Inc.

Juniper® is a registered trademark of Juniper Networks, Inc.