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study-python
study-python PublicThis project is used to stroe some demos examples when study python
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riscv-dv
riscv-dv PublicForked from chipsalliance/riscv-dv
SV/UVM based instruction generator for RISC-V processor verification
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ibex
ibex PublicForked from lowRISC/ibex
Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
SystemVerilog
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