| 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
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| 2 | /* |
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| 3 | * Copyright (C) 2021-2024 Advanced Micro Devices, Inc. |
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| 4 | */ |
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| 5 | #ifndef _AMD_APML_H_ |
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| 6 | #define _AMD_APML_H_ |
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| 7 | |
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| 8 | #include <linux/types.h> |
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| 9 | |
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| 10 | /* Mailbox data size for data_in and data_out */ |
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| 11 | #define AMD_SBI_MB_DATA_SIZE 4 |
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| 12 | |
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| 13 | struct apml_mbox_msg { |
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| 14 | /* |
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| 15 | * Mailbox Message ID |
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| 16 | */ |
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| 17 | __u32 cmd; |
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| 18 | /* |
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| 19 | * [0]...[3] mailbox 32bit input/output data |
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| 20 | */ |
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| 21 | __u32 mb_in_out; |
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| 22 | /* |
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| 23 | * Error code is returned in case of soft mailbox error |
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| 24 | */ |
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| 25 | __u32 fw_ret_code; |
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| 26 | }; |
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| 27 | |
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| 28 | struct apml_cpuid_msg { |
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| 29 | /* |
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| 30 | * CPUID input |
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| 31 | * [0]...[3] cpuid func, |
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| 32 | * [4][5] cpuid: thread |
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| 33 | * [6] cpuid: ext function & read eax/ebx or ecx/edx |
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| 34 | * [7:0] -> bits [7:4] -> ext function & |
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| 35 | * bit [0] read eax/ebx or ecx/edx |
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| 36 | * CPUID output |
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| 37 | */ |
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| 38 | __u64 cpu_in_out; |
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| 39 | /* |
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| 40 | * Status code for CPUID read |
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| 41 | */ |
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| 42 | __u32 fw_ret_code; |
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| 43 | __u32 pad; |
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| 44 | }; |
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| 45 | |
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| 46 | struct apml_mcamsr_msg { |
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| 47 | /* |
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| 48 | * MCAMSR input |
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| 49 | * [0]...[3] mca msr func, |
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| 50 | * [4][5] thread |
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| 51 | * MCAMSR output |
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| 52 | */ |
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| 53 | __u64 mcamsr_in_out; |
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| 54 | /* |
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| 55 | * Status code for MCA/MSR access |
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| 56 | */ |
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| 57 | __u32 fw_ret_code; |
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| 58 | __u32 pad; |
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| 59 | }; |
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| 60 | |
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| 61 | struct apml_reg_xfer_msg { |
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| 62 | /* |
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| 63 | * RMI register address offset |
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| 64 | */ |
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| 65 | __u16 reg_addr; |
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| 66 | /* |
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| 67 | * Register data for read/write |
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| 68 | */ |
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| 69 | __u8 data_in_out; |
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| 70 | /* |
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| 71 | * Register read or write |
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| 72 | */ |
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| 73 | __u8 rflag; |
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| 74 | }; |
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| 75 | |
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| 76 | /* |
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| 77 | * AMD sideband interface base IOCTL |
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| 78 | */ |
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| 79 | #define SB_BASE_IOCTL_NR 0xF9 |
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| 80 | |
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| 81 | /** |
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| 82 | * DOC: SBRMI_IOCTL_MBOX_CMD |
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| 83 | * |
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| 84 | * @Parameters |
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| 85 | * |
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| 86 | * @struct apml_mbox_msg |
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| 87 | * Pointer to the &struct apml_mbox_msg that will contain the protocol |
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| 88 | * information |
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| 89 | * |
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| 90 | * @Description |
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| 91 | * IOCTL command for APML messages using generic _IOWR |
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| 92 | * The IOCTL provides userspace access to AMD sideband mailbox protocol |
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| 93 | * - Mailbox message read/write(0x0~0xFF) |
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| 94 | * - returning "-EFAULT" if none of the above |
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| 95 | * "-EPROTOTYPE" error is returned to provide additional error details |
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| 96 | */ |
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| 97 | #define SBRMI_IOCTL_MBOX_CMD _IOWR(SB_BASE_IOCTL_NR, 0, struct apml_mbox_msg) |
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| 98 | |
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| 99 | /** |
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| 100 | * DOC: SBRMI_IOCTL_CPUID_CMD |
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| 101 | * |
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| 102 | * @Parameters |
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| 103 | * |
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| 104 | * @struct apml_cpuid_msg |
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| 105 | * Pointer to the &struct apml_cpuid_msg that will contain the protocol |
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| 106 | * information |
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| 107 | * |
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| 108 | * @Description |
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| 109 | * IOCTL command for APML messages using generic _IOWR |
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| 110 | * The IOCTL provides userspace access to AMD sideband cpuid protocol |
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| 111 | * - CPUID protocol to get CPU details for Function/Ext Function |
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| 112 | * at thread level |
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| 113 | * - returning "-EFAULT" if none of the above |
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| 114 | * "-EPROTOTYPE" error is returned to provide additional error details |
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| 115 | */ |
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| 116 | #define SBRMI_IOCTL_CPUID_CMD _IOWR(SB_BASE_IOCTL_NR, 1, struct apml_cpuid_msg) |
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| 117 | |
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| 118 | /** |
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| 119 | * DOC: SBRMI_IOCTL_MCAMSR_CMD |
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| 120 | * |
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| 121 | * @Parameters |
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| 122 | * |
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| 123 | * @struct apml_mcamsr_msg |
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| 124 | * Pointer to the &struct apml_mcamsr_msg that will contain the protocol |
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| 125 | * information |
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| 126 | * |
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| 127 | * @Description |
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| 128 | * IOCTL command for APML messages using generic _IOWR |
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| 129 | * The IOCTL provides userspace access to AMD sideband MCAMSR protocol |
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| 130 | * - MCAMSR protocol to get MCA bank details for Function at thread level |
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| 131 | * - returning "-EFAULT" if none of the above |
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| 132 | * "-EPROTOTYPE" error is returned to provide additional error details |
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| 133 | */ |
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| 134 | #define SBRMI_IOCTL_MCAMSR_CMD _IOWR(SB_BASE_IOCTL_NR, 2, struct apml_mcamsr_msg) |
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| 135 | |
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| 136 | /** |
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| 137 | * DOC: SBRMI_IOCTL_REG_XFER_CMD |
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| 138 | * |
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| 139 | * @Parameters |
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| 140 | * |
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| 141 | * @struct apml_reg_xfer_msg |
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| 142 | * Pointer to the &struct apml_reg_xfer_msg that will contain the protocol |
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| 143 | * information |
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| 144 | * |
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| 145 | * @Description |
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| 146 | * IOCTL command for APML messages using generic _IOWR |
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| 147 | * The IOCTL provides userspace access to AMD sideband register xfer protocol |
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| 148 | * - Register xfer protocol to get/set hardware register for given offset |
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| 149 | */ |
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| 150 | #define SBRMI_IOCTL_REG_XFER_CMD _IOWR(SB_BASE_IOCTL_NR, 3, struct apml_reg_xfer_msg) |
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| 151 | |
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| 152 | #endif /*_AMD_APML_H_*/ |
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| 153 | |
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