1/* SPDX-License-Identifier: LGPL-2.1 WITH Linux-syscall-note */
2/* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
3#ifndef _USR_IDXD_H_
4#define _USR_IDXD_H_
5
6#ifdef __KERNEL__
7#include <linux/types.h>
8#else
9#include <stdint.h>
10#endif
11
12/* Driver command error status */
13enum idxd_scmd_stat {
14 IDXD_SCMD_DEV_ENABLED = 0x80000010,
15 IDXD_SCMD_DEV_NOT_ENABLED = 0x80000020,
16 IDXD_SCMD_WQ_ENABLED = 0x80000021,
17 IDXD_SCMD_DEV_DMA_ERR = 0x80020000,
18 IDXD_SCMD_WQ_NO_GRP = 0x80030000,
19 IDXD_SCMD_WQ_NO_NAME = 0x80040000,
20 IDXD_SCMD_WQ_NO_SVM = 0x80050000,
21 IDXD_SCMD_WQ_NO_THRESH = 0x80060000,
22 IDXD_SCMD_WQ_PORTAL_ERR = 0x80070000,
23 IDXD_SCMD_WQ_RES_ALLOC_ERR = 0x80080000,
24 IDXD_SCMD_PERCPU_ERR = 0x80090000,
25 IDXD_SCMD_DMA_CHAN_ERR = 0x800a0000,
26 IDXD_SCMD_CDEV_ERR = 0x800b0000,
27 IDXD_SCMD_WQ_NO_SWQ_SUPPORT = 0x800c0000,
28 IDXD_SCMD_WQ_NONE_CONFIGURED = 0x800d0000,
29 IDXD_SCMD_WQ_NO_SIZE = 0x800e0000,
30 IDXD_SCMD_WQ_NO_PRIV = 0x800f0000,
31 IDXD_SCMD_WQ_IRQ_ERR = 0x80100000,
32 IDXD_SCMD_WQ_USER_NO_IOMMU = 0x80110000,
33 IDXD_SCMD_DEV_EVL_ERR = 0x80120000,
34 IDXD_SCMD_WQ_NO_DRV_NAME = 0x80200000,
35};
36
37#define IDXD_SCMD_SOFTERR_MASK 0x80000000
38#define IDXD_SCMD_SOFTERR_SHIFT 16
39
40/* Descriptor flags */
41#define IDXD_OP_FLAG_FENCE 0x0001
42#define IDXD_OP_FLAG_BOF 0x0002
43#define IDXD_OP_FLAG_CRAV 0x0004
44#define IDXD_OP_FLAG_RCR 0x0008
45#define IDXD_OP_FLAG_RCI 0x0010
46#define IDXD_OP_FLAG_CRSTS 0x0020
47#define IDXD_OP_FLAG_CR 0x0080
48#define IDXD_OP_FLAG_CC 0x0100
49#define IDXD_OP_FLAG_ADDR1_TCS 0x0200
50#define IDXD_OP_FLAG_ADDR2_TCS 0x0400
51#define IDXD_OP_FLAG_ADDR3_TCS 0x0800
52#define IDXD_OP_FLAG_CR_TCS 0x1000
53#define IDXD_OP_FLAG_STORD 0x2000
54#define IDXD_OP_FLAG_DRDBK 0x4000
55#define IDXD_OP_FLAG_DSTS 0x8000
56
57/* IAX */
58#define IDXD_OP_FLAG_RD_SRC2_AECS 0x010000
59#define IDXD_OP_FLAG_RD_SRC2_2ND 0x020000
60#define IDXD_OP_FLAG_WR_SRC2_AECS_COMP 0x040000
61#define IDXD_OP_FLAG_WR_SRC2_AECS_OVFL 0x080000
62#define IDXD_OP_FLAG_SRC2_STS 0x100000
63#define IDXD_OP_FLAG_CRC_RFC3720 0x200000
64
65/* Opcode */
66enum dsa_opcode {
67 DSA_OPCODE_NOOP = 0,
68 DSA_OPCODE_BATCH,
69 DSA_OPCODE_DRAIN,
70 DSA_OPCODE_MEMMOVE,
71 DSA_OPCODE_MEMFILL,
72 DSA_OPCODE_COMPARE,
73 DSA_OPCODE_COMPVAL,
74 DSA_OPCODE_CR_DELTA,
75 DSA_OPCODE_AP_DELTA,
76 DSA_OPCODE_DUALCAST,
77 DSA_OPCODE_TRANSL_FETCH,
78 DSA_OPCODE_CRCGEN = 0x10,
79 DSA_OPCODE_COPY_CRC,
80 DSA_OPCODE_DIF_CHECK,
81 DSA_OPCODE_DIF_INS,
82 DSA_OPCODE_DIF_STRP,
83 DSA_OPCODE_DIF_UPDT,
84 DSA_OPCODE_DIX_GEN = 0x17,
85 DSA_OPCODE_CFLUSH = 0x20,
86};
87
88enum iax_opcode {
89 IAX_OPCODE_NOOP = 0,
90 IAX_OPCODE_DRAIN = 2,
91 IAX_OPCODE_MEMMOVE,
92 IAX_OPCODE_DECOMPRESS = 0x42,
93 IAX_OPCODE_COMPRESS,
94 IAX_OPCODE_CRC64,
95 IAX_OPCODE_ZERO_DECOMP_32 = 0x48,
96 IAX_OPCODE_ZERO_DECOMP_16,
97 IAX_OPCODE_ZERO_COMP_32 = 0x4c,
98 IAX_OPCODE_ZERO_COMP_16,
99 IAX_OPCODE_SCAN = 0x50,
100 IAX_OPCODE_SET_MEMBER,
101 IAX_OPCODE_EXTRACT,
102 IAX_OPCODE_SELECT,
103 IAX_OPCODE_RLE_BURST,
104 IAX_OPCODE_FIND_UNIQUE,
105 IAX_OPCODE_EXPAND,
106};
107
108/* Completion record status */
109enum dsa_completion_status {
110 DSA_COMP_NONE = 0,
111 DSA_COMP_SUCCESS,
112 DSA_COMP_SUCCESS_PRED,
113 DSA_COMP_PAGE_FAULT_NOBOF,
114 DSA_COMP_PAGE_FAULT_IR,
115 DSA_COMP_BATCH_FAIL,
116 DSA_COMP_BATCH_PAGE_FAULT,
117 DSA_COMP_DR_OFFSET_NOINC,
118 DSA_COMP_DR_OFFSET_ERANGE,
119 DSA_COMP_DIF_ERR,
120 DSA_COMP_BAD_OPCODE = 0x10,
121 DSA_COMP_INVALID_FLAGS,
122 DSA_COMP_NOZERO_RESERVE,
123 DSA_COMP_XFER_ERANGE,
124 DSA_COMP_DESC_CNT_ERANGE,
125 DSA_COMP_DR_ERANGE,
126 DSA_COMP_OVERLAP_BUFFERS,
127 DSA_COMP_DCAST_ERR,
128 DSA_COMP_DESCLIST_ALIGN,
129 DSA_COMP_INT_HANDLE_INVAL,
130 DSA_COMP_CRA_XLAT,
131 DSA_COMP_CRA_ALIGN,
132 DSA_COMP_ADDR_ALIGN,
133 DSA_COMP_PRIV_BAD,
134 DSA_COMP_TRAFFIC_CLASS_CONF,
135 DSA_COMP_PFAULT_RDBA,
136 DSA_COMP_HW_ERR1,
137 DSA_COMP_HW_ERR_DRB,
138 DSA_COMP_TRANSLATION_FAIL,
139 DSA_COMP_DRAIN_EVL = 0x26,
140 DSA_COMP_BATCH_EVL_ERR,
141};
142
143enum iax_completion_status {
144 IAX_COMP_NONE = 0,
145 IAX_COMP_SUCCESS,
146 IAX_COMP_PAGE_FAULT_IR = 0x04,
147 IAX_COMP_ANALYTICS_ERROR = 0x0a,
148 IAX_COMP_OUTBUF_OVERFLOW,
149 IAX_COMP_BAD_OPCODE = 0x10,
150 IAX_COMP_INVALID_FLAGS,
151 IAX_COMP_NOZERO_RESERVE,
152 IAX_COMP_INVALID_SIZE,
153 IAX_COMP_OVERLAP_BUFFERS = 0x16,
154 IAX_COMP_INT_HANDLE_INVAL = 0x19,
155 IAX_COMP_CRA_XLAT,
156 IAX_COMP_CRA_ALIGN,
157 IAX_COMP_ADDR_ALIGN,
158 IAX_COMP_PRIV_BAD,
159 IAX_COMP_TRAFFIC_CLASS_CONF,
160 IAX_COMP_PFAULT_RDBA,
161 IAX_COMP_HW_ERR1,
162 IAX_COMP_HW_ERR_DRB,
163 IAX_COMP_TRANSLATION_FAIL,
164 IAX_COMP_PRS_TIMEOUT,
165 IAX_COMP_WATCHDOG,
166 IAX_COMP_INVALID_COMP_FLAG = 0x30,
167 IAX_COMP_INVALID_FILTER_FLAG,
168 IAX_COMP_INVALID_INPUT_SIZE,
169 IAX_COMP_INVALID_NUM_ELEMS,
170 IAX_COMP_INVALID_SRC1_WIDTH,
171 IAX_COMP_INVALID_INVERT_OUT,
172};
173
174#define DSA_COMP_STATUS_MASK 0x7f
175#define DSA_COMP_STATUS_WRITE 0x80
176#define DSA_COMP_STATUS(status) ((status) & DSA_COMP_STATUS_MASK)
177
178struct dsa_hw_desc {
179 uint32_t pasid:20;
180 uint32_t rsvd:11;
181 uint32_t priv:1;
182 uint32_t flags:24;
183 uint32_t opcode:8;
184 uint64_t completion_addr;
185 union {
186 uint64_t src_addr;
187 uint64_t rdback_addr;
188 uint64_t pattern;
189 uint64_t desc_list_addr;
190 uint64_t pattern_lower;
191 uint64_t transl_fetch_addr;
192 };
193 union {
194 uint64_t dst_addr;
195 uint64_t rdback_addr2;
196 uint64_t src2_addr;
197 uint64_t comp_pattern;
198 };
199 union {
200 uint32_t xfer_size;
201 uint32_t desc_count;
202 uint32_t region_size;
203 };
204 uint16_t int_handle;
205 uint16_t rsvd1;
206 union {
207 uint8_t expected_res;
208 /* create delta record */
209 struct {
210 uint64_t delta_addr;
211 uint32_t max_delta_size;
212 uint32_t delt_rsvd;
213 uint8_t expected_res_mask;
214 };
215 uint32_t delta_rec_size;
216 uint64_t dest2;
217 /* CRC */
218 struct {
219 uint32_t crc_seed;
220 uint32_t crc_rsvd;
221 uint64_t seed_addr;
222 };
223 /* DIF check or strip */
224 struct {
225 uint8_t src_dif_flags;
226 uint8_t dif_chk_res;
227 uint8_t dif_chk_flags;
228 uint8_t dif_chk_res2[5];
229 uint32_t chk_ref_tag_seed;
230 uint16_t chk_app_tag_mask;
231 uint16_t chk_app_tag_seed;
232 };
233 /* DIF insert */
234 struct {
235 uint8_t dif_ins_res;
236 uint8_t dest_dif_flag;
237 uint8_t dif_ins_flags;
238 uint8_t dif_ins_res2[13];
239 uint32_t ins_ref_tag_seed;
240 uint16_t ins_app_tag_mask;
241 uint16_t ins_app_tag_seed;
242 };
243 /* DIF update */
244 struct {
245 uint8_t src_upd_flags;
246 uint8_t upd_dest_flags;
247 uint8_t dif_upd_flags;
248 uint8_t dif_upd_res[5];
249 uint32_t src_ref_tag_seed;
250 uint16_t src_app_tag_mask;
251 uint16_t src_app_tag_seed;
252 uint32_t dest_ref_tag_seed;
253 uint16_t dest_app_tag_mask;
254 uint16_t dest_app_tag_seed;
255 };
256
257 /* Fill */
258 uint64_t pattern_upper;
259
260 /* Translation fetch */
261 struct {
262 uint64_t transl_fetch_res;
263 uint32_t region_stride;
264 };
265
266 /* DIX generate */
267 struct {
268 uint8_t dix_gen_res;
269 uint8_t dest_dif_flags;
270 uint8_t dif_flags;
271 uint8_t dix_gen_res2[13];
272 uint32_t ref_tag_seed;
273 uint16_t app_tag_mask;
274 uint16_t app_tag_seed;
275 };
276
277 uint8_t op_specific[24];
278 };
279} __attribute__((packed));
280
281struct iax_hw_desc {
282 uint32_t pasid:20;
283 uint32_t rsvd:11;
284 uint32_t priv:1;
285 uint32_t flags:24;
286 uint32_t opcode:8;
287 uint64_t completion_addr;
288 uint64_t src1_addr;
289 uint64_t dst_addr;
290 uint32_t src1_size;
291 uint16_t int_handle;
292 union {
293 uint16_t compr_flags;
294 uint16_t decompr_flags;
295 };
296 uint64_t src2_addr;
297 uint32_t max_dst_size;
298 uint32_t src2_size;
299 uint32_t filter_flags;
300 uint32_t num_inputs;
301} __attribute__((packed));
302
303struct dsa_raw_desc {
304 uint64_t field[8];
305} __attribute__((packed));
306
307/*
308 * The status field will be modified by hardware, therefore it should be
309 * volatile and prevent the compiler from optimize the read.
310 */
311struct dsa_completion_record {
312 volatile uint8_t status;
313 union {
314 uint8_t result;
315 uint8_t dif_status;
316 };
317 uint8_t fault_info;
318 uint8_t rsvd;
319 union {
320 uint32_t bytes_completed;
321 uint32_t descs_completed;
322 };
323 uint64_t fault_addr;
324 union {
325 /* common record */
326 struct {
327 uint32_t invalid_flags:24;
328 uint32_t rsvd2:8;
329 };
330
331 uint32_t delta_rec_size;
332 uint64_t crc_val;
333
334 /* DIF check & strip */
335 struct {
336 uint32_t dif_chk_ref_tag;
337 uint16_t dif_chk_app_tag_mask;
338 uint16_t dif_chk_app_tag;
339 };
340
341 /* DIF insert */
342 struct {
343 uint64_t dif_ins_res;
344 uint32_t dif_ins_ref_tag;
345 uint16_t dif_ins_app_tag_mask;
346 uint16_t dif_ins_app_tag;
347 };
348
349 /* DIF update */
350 struct {
351 uint32_t dif_upd_src_ref_tag;
352 uint16_t dif_upd_src_app_tag_mask;
353 uint16_t dif_upd_src_app_tag;
354 uint32_t dif_upd_dest_ref_tag;
355 uint16_t dif_upd_dest_app_tag_mask;
356 uint16_t dif_upd_dest_app_tag;
357 };
358
359 /* DIX generate */
360 struct {
361 uint64_t dix_gen_res;
362 uint32_t dix_ref_tag;
363 uint16_t dix_app_tag_mask;
364 uint16_t dix_app_tag;
365 };
366
367 uint8_t op_specific[16];
368 };
369} __attribute__((packed));
370
371struct dsa_raw_completion_record {
372 uint64_t field[4];
373} __attribute__((packed));
374
375struct iax_completion_record {
376 volatile uint8_t status;
377 uint8_t error_code;
378 uint8_t fault_info;
379 uint8_t rsvd;
380 uint32_t bytes_completed;
381 uint64_t fault_addr;
382 uint32_t invalid_flags;
383 uint32_t rsvd2;
384 uint32_t output_size;
385 uint8_t output_bits;
386 uint8_t rsvd3;
387 uint16_t xor_csum;
388 uint32_t crc;
389 uint32_t min;
390 uint32_t max;
391 uint32_t sum;
392 uint64_t rsvd4[2];
393} __attribute__((packed));
394
395struct iax_raw_completion_record {
396 uint64_t field[8];
397} __attribute__((packed));
398
399#endif
400

source code of linux/include/uapi/linux/idxd.h

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