| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright (C) 2019 Cadence Design Systems Inc. |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __PHY_DP_H_ |
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| 7 | #define __PHY_DP_H_ |
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| 8 | |
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| 9 | #include <linux/types.h> |
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| 10 | |
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| 11 | #define PHY_SUBMODE_DP 0 |
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| 12 | #define PHY_SUBMODE_EDP 1 |
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| 13 | |
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| 14 | /** |
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| 15 | * struct phy_configure_opts_dp - DisplayPort PHY configuration set |
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| 16 | * |
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| 17 | * This structure is used to represent the configuration state of a |
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| 18 | * DisplayPort phy. |
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| 19 | */ |
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| 20 | struct phy_configure_opts_dp { |
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| 21 | /** |
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| 22 | * @link_rate: |
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| 23 | * |
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| 24 | * Link Rate, in Mb/s, of the main link. |
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| 25 | * |
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| 26 | * Allowed values: 1620, 2160, 2430, 2700, 3240, 4320, 5400, 8100 Mb/s |
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| 27 | */ |
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| 28 | unsigned int link_rate; |
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| 29 | |
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| 30 | /** |
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| 31 | * @lanes: |
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| 32 | * |
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| 33 | * Number of active, consecutive, data lanes, starting from |
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| 34 | * lane 0, used for the transmissions on main link. |
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| 35 | * |
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| 36 | * Allowed values: 1, 2, 4 |
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| 37 | */ |
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| 38 | unsigned int lanes; |
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| 39 | |
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| 40 | /** |
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| 41 | * @voltage: |
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| 42 | * |
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| 43 | * Voltage swing levels, as specified by DisplayPort specification, |
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| 44 | * to be used by particular lanes. One value per lane. |
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| 45 | * voltage[0] is for lane 0, voltage[1] is for lane 1, etc. |
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| 46 | * |
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| 47 | * Maximum value: 3 |
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| 48 | */ |
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| 49 | unsigned int voltage[4]; |
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| 50 | |
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| 51 | /** |
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| 52 | * @pre: |
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| 53 | * |
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| 54 | * Pre-emphasis levels, as specified by DisplayPort specification, to be |
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| 55 | * used by particular lanes. One value per lane. |
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| 56 | * |
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| 57 | * Maximum value: 3 |
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| 58 | */ |
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| 59 | unsigned int pre[4]; |
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| 60 | |
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| 61 | /** |
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| 62 | * @ssc: |
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| 63 | * |
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| 64 | * Flag indicating, whether or not to enable spread-spectrum clocking. |
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| 65 | * |
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| 66 | */ |
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| 67 | u8 ssc : 1; |
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| 68 | |
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| 69 | /** |
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| 70 | * @set_rate: |
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| 71 | * |
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| 72 | * Flag indicating, whether or not reconfigure link rate and SSC to |
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| 73 | * requested values. |
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| 74 | * |
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| 75 | */ |
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| 76 | u8 set_rate : 1; |
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| 77 | |
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| 78 | /** |
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| 79 | * @set_lanes: |
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| 80 | * |
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| 81 | * Flag indicating, whether or not reconfigure lane count to |
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| 82 | * requested value. |
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| 83 | * |
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| 84 | */ |
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| 85 | u8 set_lanes : 1; |
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| 86 | |
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| 87 | /** |
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| 88 | * @set_voltages: |
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| 89 | * |
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| 90 | * Flag indicating, whether or not reconfigure voltage swing |
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| 91 | * and pre-emphasis to requested values. Only lanes specified |
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| 92 | * by "lanes" parameter will be affected. |
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| 93 | * |
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| 94 | */ |
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| 95 | u8 set_voltages : 1; |
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| 96 | }; |
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| 97 | |
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| 98 | #endif /* __PHY_DP_H_ */ |
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| 99 | |
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