1/*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DRIVER_H
34#define MLX5_DRIVER_H
35
36#include <linux/kernel.h>
37#include <linux/completion.h>
38#include <linux/pci.h>
39#include <linux/pci-tph.h>
40#include <linux/irq.h>
41#include <linux/spinlock_types.h>
42#include <linux/semaphore.h>
43#include <linux/slab.h>
44#include <linux/vmalloc.h>
45#include <linux/xarray.h>
46#include <linux/workqueue.h>
47#include <linux/mempool.h>
48#include <linux/interrupt.h>
49#include <linux/notifier.h>
50#include <linux/refcount.h>
51#include <linux/auxiliary_bus.h>
52#include <linux/mutex.h>
53
54#include <linux/mlx5/device.h>
55#include <linux/mlx5/doorbell.h>
56#include <linux/mlx5/eq.h>
57#include <linux/timecounter.h>
58#include <net/devlink.h>
59
60#define MLX5_ADEV_NAME "mlx5_core"
61
62#define MLX5_IRQ_EQ_CTRL (U8_MAX)
63
64enum {
65 MLX5_BOARD_ID_LEN = 64,
66};
67
68enum {
69 MLX5_CMD_WQ_MAX_NAME = 32,
70};
71
72enum {
73 CMD_OWNER_SW = 0x0,
74 CMD_OWNER_HW = 0x1,
75 CMD_STATUS_SUCCESS = 0,
76};
77
78enum mlx5_sqp_t {
79 MLX5_SQP_SMI = 0,
80 MLX5_SQP_GSI = 1,
81 MLX5_SQP_IEEE_1588 = 2,
82 MLX5_SQP_SNIFFER = 3,
83 MLX5_SQP_SYNC_UMR = 4,
84};
85
86enum {
87 MLX5_MAX_PORTS = 8,
88};
89
90enum {
91 MLX5_ATOMIC_MODE_OFFSET = 16,
92 MLX5_ATOMIC_MODE_IB_COMP = 1,
93 MLX5_ATOMIC_MODE_CX = 2,
94 MLX5_ATOMIC_MODE_8B = 3,
95 MLX5_ATOMIC_MODE_16B = 4,
96 MLX5_ATOMIC_MODE_32B = 5,
97 MLX5_ATOMIC_MODE_64B = 6,
98 MLX5_ATOMIC_MODE_128B = 7,
99 MLX5_ATOMIC_MODE_256B = 8,
100};
101
102enum {
103 MLX5_REG_SBPR = 0xb001,
104 MLX5_REG_SBCM = 0xb002,
105 MLX5_REG_QPTS = 0x4002,
106 MLX5_REG_QETCR = 0x4005,
107 MLX5_REG_QTCT = 0x400a,
108 MLX5_REG_QPDPM = 0x4013,
109 MLX5_REG_QCAM = 0x4019,
110 MLX5_REG_DCBX_PARAM = 0x4020,
111 MLX5_REG_DCBX_APP = 0x4021,
112 MLX5_REG_FPGA_CAP = 0x4022,
113 MLX5_REG_FPGA_CTRL = 0x4023,
114 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
115 MLX5_REG_CORE_DUMP = 0x402e,
116 MLX5_REG_PCAP = 0x5001,
117 MLX5_REG_PMTU = 0x5003,
118 MLX5_REG_PTYS = 0x5004,
119 MLX5_REG_PAOS = 0x5006,
120 MLX5_REG_PFCC = 0x5007,
121 MLX5_REG_PPCNT = 0x5008,
122 MLX5_REG_PPTB = 0x500b,
123 MLX5_REG_PBMC = 0x500c,
124 MLX5_REG_PMAOS = 0x5012,
125 MLX5_REG_PUDE = 0x5009,
126 MLX5_REG_PMPE = 0x5010,
127 MLX5_REG_PELC = 0x500e,
128 MLX5_REG_PVLC = 0x500f,
129 MLX5_REG_PCMR = 0x5041,
130 MLX5_REG_PDDR = 0x5031,
131 MLX5_REG_PMLP = 0x5002,
132 MLX5_REG_PPLM = 0x5023,
133 MLX5_REG_PPHCR = 0x503E,
134 MLX5_REG_PCAM = 0x507f,
135 MLX5_REG_NODE_DESC = 0x6001,
136 MLX5_REG_HOST_ENDIANNESS = 0x7004,
137 MLX5_REG_MTCAP = 0x9009,
138 MLX5_REG_MTMP = 0x900A,
139 MLX5_REG_MCIA = 0x9014,
140 MLX5_REG_MNVDA = 0x9024,
141 MLX5_REG_MFRL = 0x9028,
142 MLX5_REG_MLCR = 0x902b,
143 MLX5_REG_MRTC = 0x902d,
144 MLX5_REG_MTRC_CAP = 0x9040,
145 MLX5_REG_MTRC_CONF = 0x9041,
146 MLX5_REG_MTRC_STDB = 0x9042,
147 MLX5_REG_MTRC_CTRL = 0x9043,
148 MLX5_REG_MPEIN = 0x9050,
149 MLX5_REG_MPCNT = 0x9051,
150 MLX5_REG_MTPPS = 0x9053,
151 MLX5_REG_MTPPSE = 0x9054,
152 MLX5_REG_MTUTC = 0x9055,
153 MLX5_REG_MPEGC = 0x9056,
154 MLX5_REG_MPIR = 0x9059,
155 MLX5_REG_MCQS = 0x9060,
156 MLX5_REG_MCQI = 0x9061,
157 MLX5_REG_MCC = 0x9062,
158 MLX5_REG_MCDA = 0x9063,
159 MLX5_REG_MCAM = 0x907f,
160 MLX5_REG_MSECQ = 0x9155,
161 MLX5_REG_MSEES = 0x9156,
162 MLX5_REG_MIRC = 0x9162,
163 MLX5_REG_MTPTM = 0x9180,
164 MLX5_REG_MTCTR = 0x9181,
165 MLX5_REG_MRTCQ = 0x9182,
166 MLX5_REG_SBCAM = 0xB01F,
167 MLX5_REG_RESOURCE_DUMP = 0xC000,
168 MLX5_REG_NIC_CAP = 0xC00D,
169 MLX5_REG_DTOR = 0xC00E,
170 MLX5_REG_VHCA_ICM_CTRL = 0xC010,
171};
172
173enum mlx5_qpts_trust_state {
174 MLX5_QPTS_TRUST_PCP = 1,
175 MLX5_QPTS_TRUST_DSCP = 2,
176};
177
178enum mlx5_dcbx_oper_mode {
179 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0,
180 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
181};
182
183enum {
184 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
185 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
186 MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
187 MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
188};
189
190enum mlx5_page_fault_resume_flags {
191 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
192 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
193 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
194 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
195};
196
197enum dbg_rsc_type {
198 MLX5_DBG_RSC_QP,
199 MLX5_DBG_RSC_EQ,
200 MLX5_DBG_RSC_CQ,
201};
202
203enum port_state_policy {
204 MLX5_POLICY_DOWN = 0,
205 MLX5_POLICY_UP = 1,
206 MLX5_POLICY_FOLLOW = 2,
207 MLX5_POLICY_INVALID = 0xffffffff
208};
209
210enum mlx5_coredev_type {
211 MLX5_COREDEV_PF,
212 MLX5_COREDEV_VF,
213 MLX5_COREDEV_SF,
214};
215
216struct mlx5_field_desc {
217 int i;
218};
219
220struct mlx5_rsc_debug {
221 struct mlx5_core_dev *dev;
222 void *object;
223 enum dbg_rsc_type type;
224 struct dentry *root;
225 struct mlx5_field_desc fields[];
226};
227
228enum mlx5_dev_event {
229 MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
230 MLX5_DEV_EVENT_PORT_AFFINITY = 129,
231 MLX5_DEV_EVENT_MULTIPORT_ESW = 130,
232};
233
234enum mlx5_port_status {
235 MLX5_PORT_UP = 1,
236 MLX5_PORT_DOWN = 2,
237};
238
239enum mlx5_cmdif_state {
240 MLX5_CMDIF_STATE_UNINITIALIZED,
241 MLX5_CMDIF_STATE_UP,
242 MLX5_CMDIF_STATE_DOWN,
243};
244
245struct mlx5_cmd_first {
246 __be32 data[4];
247};
248
249struct mlx5_cmd_msg {
250 struct list_head list;
251 struct cmd_msg_cache *parent;
252 u32 len;
253 struct mlx5_cmd_first first;
254 struct mlx5_cmd_mailbox *next;
255};
256
257struct mlx5_cmd_debug {
258 struct dentry *dbg_root;
259 void *in_msg;
260 void *out_msg;
261 u8 status;
262 u16 inlen;
263 u16 outlen;
264};
265
266struct cmd_msg_cache {
267 /* protect block chain allocations
268 */
269 spinlock_t lock;
270 struct list_head head;
271 unsigned int max_inbox_size;
272 unsigned int num_ent;
273};
274
275enum {
276 MLX5_NUM_COMMAND_CACHES = 5,
277};
278
279struct mlx5_cmd_stats {
280 u64 sum;
281 u64 n;
282 /* number of times command failed */
283 u64 failed;
284 /* number of times command failed on bad status returned by FW */
285 u64 failed_mbox_status;
286 /* last command failed returned errno */
287 u32 last_failed_errno;
288 /* last bad status returned by FW */
289 u8 last_failed_mbox_status;
290 /* last command failed syndrome returned by FW */
291 u32 last_failed_syndrome;
292 struct dentry *root;
293 /* protect command average calculations */
294 spinlock_t lock;
295};
296
297struct mlx5_cmd {
298 struct mlx5_nb nb;
299
300 /* members which needs to be queried or reinitialized each reload */
301 struct {
302 u16 cmdif_rev;
303 u8 log_sz;
304 u8 log_stride;
305 int max_reg_cmds;
306 unsigned long bitmask;
307 struct semaphore sem;
308 struct semaphore pages_sem;
309 struct semaphore throttle_sem;
310 struct semaphore unprivileged_sem;
311 struct xarray privileged_uids;
312 } vars;
313 enum mlx5_cmdif_state state;
314 void *cmd_alloc_buf;
315 dma_addr_t alloc_dma;
316 int alloc_size;
317 void *cmd_buf;
318 dma_addr_t dma;
319
320 /* protect command queue allocations
321 */
322 spinlock_t alloc_lock;
323
324 /* protect token allocations
325 */
326 spinlock_t token_lock;
327 u8 token;
328 char wq_name[MLX5_CMD_WQ_MAX_NAME];
329 struct workqueue_struct *wq;
330 int mode;
331 u16 allowed_opcode;
332 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
333 struct dma_pool *pool;
334 struct mlx5_cmd_debug dbg;
335 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
336 int checksum_disabled;
337 struct xarray stats;
338};
339
340struct mlx5_cmd_mailbox {
341 void *buf;
342 dma_addr_t dma;
343 struct mlx5_cmd_mailbox *next;
344};
345
346struct mlx5_buf_list {
347 void *buf;
348 dma_addr_t map;
349};
350
351struct mlx5_frag_buf {
352 struct mlx5_buf_list *frags;
353 int npages;
354 int size;
355 u8 page_shift;
356};
357
358struct mlx5_frag_buf_ctrl {
359 struct mlx5_buf_list *frags;
360 u32 sz_m1;
361 u16 frag_sz_m1;
362 u16 strides_offset;
363 u8 log_sz;
364 u8 log_stride;
365 u8 log_frag_strides;
366};
367
368struct mlx5_core_psv {
369 u32 psv_idx;
370 struct psv_layout {
371 u32 pd;
372 u16 syndrome;
373 u16 reserved;
374 u16 bg;
375 u16 app_tag;
376 u32 ref_tag;
377 } psv;
378};
379
380struct mlx5_core_sig_ctx {
381 struct mlx5_core_psv psv_memory;
382 struct mlx5_core_psv psv_wire;
383 struct ib_sig_err err_item;
384 bool sig_status_checked;
385 bool sig_err_exists;
386 u32 sigerr_count;
387};
388
389#define MLX5_24BIT_MASK ((1 << 24) - 1)
390
391enum mlx5_res_type {
392 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
393 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
394 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
395 MLX5_RES_SRQ = 3,
396 MLX5_RES_XSRQ = 4,
397 MLX5_RES_XRQ = 5,
398};
399
400struct mlx5_core_rsc_common {
401 enum mlx5_res_type res;
402 refcount_t refcount;
403 struct completion free;
404 bool invalid;
405};
406
407struct mlx5_uars_page {
408 void __iomem *map;
409 bool wc;
410 u32 index;
411 struct list_head list;
412 unsigned int bfregs;
413 unsigned long *reg_bitmap; /* for non fast path bf regs */
414 unsigned long *fp_bitmap;
415 unsigned int reg_avail;
416 unsigned int fp_avail;
417 struct kref ref_count;
418 struct mlx5_core_dev *mdev;
419};
420
421struct mlx5_bfreg_head {
422 /* protect blue flame registers allocations */
423 struct mutex lock;
424 struct list_head list;
425};
426
427struct mlx5_bfreg_data {
428 struct mlx5_bfreg_head reg_head;
429 struct mlx5_bfreg_head wc_head;
430};
431
432struct mlx5_sq_bfreg {
433 void __iomem *map;
434 struct mlx5_uars_page *up;
435 bool wc;
436 u32 index;
437};
438
439struct mlx5_core_health {
440 struct health_buffer __iomem *health;
441 __be32 __iomem *health_counter;
442 struct timer_list timer;
443 u32 prev;
444 int miss_counter;
445 u8 synd;
446 u32 fatal_error;
447 u32 crdump_size;
448 struct workqueue_struct *wq;
449 unsigned long flags;
450 struct work_struct fatal_report_work;
451 struct work_struct report_work;
452 struct devlink_health_reporter *fw_reporter;
453 struct devlink_health_reporter *fw_fatal_reporter;
454 struct devlink_health_reporter *vnic_reporter;
455 struct delayed_work update_fw_log_ts_work;
456};
457
458enum {
459 MLX5_PF_NOTIFY_DISABLE_VF,
460 MLX5_PF_NOTIFY_ENABLE_VF,
461};
462
463struct mlx5_vf_context {
464 int enabled;
465 u64 port_guid;
466 u64 node_guid;
467 /* Valid bits are used to validate administrative guid only.
468 * Enabled after ndo_set_vf_guid
469 */
470 u8 port_guid_valid:1;
471 u8 node_guid_valid:1;
472 enum port_state_policy policy;
473 struct blocking_notifier_head notifier;
474};
475
476struct mlx5_core_sriov {
477 struct mlx5_vf_context *vfs_ctx;
478 int num_vfs;
479 u16 max_vfs;
480 u16 max_ec_vfs;
481};
482
483struct mlx5_events;
484struct mlx5_mpfs;
485struct mlx5_eswitch;
486struct mlx5_lag;
487struct mlx5_devcom_dev;
488struct mlx5_fw_reset;
489struct mlx5_eq_table;
490struct mlx5_irq_table;
491struct mlx5_sf_dev_table;
492struct mlx5_sf_hw_table;
493struct mlx5_sf_table;
494struct mlx5_crypto_dek_priv;
495
496struct mlx5_rate_limit {
497 u32 rate;
498 u32 max_burst_sz;
499 u16 typical_pkt_sz;
500};
501
502struct mlx5_rl_entry {
503 u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
504 u64 refcount;
505 u16 index;
506 u16 uid;
507 u8 dedicated : 1;
508};
509
510struct mlx5_rl_table {
511 /* protect rate limit table */
512 struct mutex rl_lock;
513 u16 max_size;
514 u32 max_rate;
515 u32 min_rate;
516 struct mlx5_rl_entry *rl_entry;
517 u64 refcount;
518};
519
520struct mlx5_core_roce {
521 struct mlx5_flow_table *ft;
522 struct mlx5_flow_group *fg;
523 struct mlx5_flow_handle *allow_rule;
524};
525
526enum {
527 MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0,
528 MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1,
529 /* Set during device detach to block any further devices
530 * creation/deletion on drivers rescan. Unset during device attach.
531 */
532 MLX5_PRIV_FLAGS_DETACH = 1 << 2,
533 MLX5_PRIV_FLAGS_SWITCH_LEGACY = 1 << 3,
534};
535
536struct mlx5_adev {
537 struct auxiliary_device adev;
538 struct mlx5_core_dev *mdev;
539 int idx;
540};
541
542struct mlx5_debugfs_entries {
543 struct dentry *dbg_root;
544 struct dentry *qp_debugfs;
545 struct dentry *eq_debugfs;
546 struct dentry *cq_debugfs;
547 struct dentry *cmdif_debugfs;
548 struct dentry *pages_debugfs;
549 struct dentry *lag_debugfs;
550};
551
552enum mlx5_func_type {
553 MLX5_PF,
554 MLX5_VF,
555 MLX5_SF,
556 MLX5_HOST_PF,
557 MLX5_EC_VF,
558 MLX5_FUNC_TYPE_NUM,
559};
560
561struct mlx5_ft_pool;
562struct mlx5_priv {
563 /* IRQ table valid only for real pci devices PF or VF */
564 struct mlx5_irq_table *irq_table;
565 struct mlx5_eq_table *eq_table;
566
567 /* pages stuff */
568 struct mlx5_nb pg_nb;
569 struct workqueue_struct *pg_wq;
570 struct xarray page_root_xa;
571 atomic_t reg_pages;
572 struct list_head free_list;
573 u32 fw_pages;
574 u32 page_counters[MLX5_FUNC_TYPE_NUM];
575 u32 fw_pages_alloc_failed;
576 u32 give_pages_dropped;
577 u32 reclaim_pages_discard;
578
579 struct mlx5_core_health health;
580 struct list_head traps;
581
582 struct mlx5_debugfs_entries dbg;
583
584 /* start: alloc staff */
585 /* protect buffer allocation according to numa node */
586 struct mutex alloc_mutex;
587 int numa_node;
588
589 struct mutex pgdir_mutex;
590 struct list_head pgdir_list;
591 /* end: alloc staff */
592
593 struct mlx5_adev **adev;
594 int adev_idx;
595 int sw_vhca_id;
596 struct mlx5_events *events;
597 struct mlx5_vhca_events *vhca_events;
598
599 struct mlx5_flow_steering *steering;
600 struct mlx5_mpfs *mpfs;
601 struct blocking_notifier_head esw_n_head;
602 struct mlx5_eswitch *eswitch;
603 struct mlx5_core_sriov sriov;
604 struct mlx5_lag *lag;
605 u32 flags;
606 struct mlx5_devcom_dev *devc;
607 struct mlx5_devcom_comp_dev *hca_devcom_comp;
608 struct mlx5_fw_reset *fw_reset;
609 struct mlx5_core_roce roce;
610 struct mlx5_fc_stats *fc_stats;
611 struct mlx5_rl_table rl_table;
612 struct mlx5_ft_pool *ft_pool;
613
614 struct mlx5_bfreg_data bfregs;
615 struct mlx5_sq_bfreg bfreg;
616#ifdef CONFIG_MLX5_SF
617 struct mlx5_nb vhca_state_nb;
618 struct blocking_notifier_head vhca_state_n_head;
619 struct notifier_block sf_dev_nb;
620 struct mlx5_sf_dev_table *sf_dev_table;
621 struct mlx5_core_dev *parent_mdev;
622#endif
623#ifdef CONFIG_MLX5_SF_MANAGER
624 struct notifier_block sf_hw_table_vhca_nb;
625 struct mlx5_sf_hw_table *sf_hw_table;
626 struct notifier_block sf_table_esw_nb;
627 struct notifier_block sf_table_vhca_nb;
628 struct notifier_block sf_table_mdev_nb;
629 struct mlx5_sf_table *sf_table;
630#endif
631 struct blocking_notifier_head lag_nh;
632};
633
634enum mlx5_device_state {
635 MLX5_DEVICE_STATE_UP = 1,
636 MLX5_DEVICE_STATE_INTERNAL_ERROR,
637};
638
639enum mlx5_interface_state {
640 MLX5_INTERFACE_STATE_UP = BIT(0),
641 MLX5_BREAK_FW_WAIT = BIT(1),
642};
643
644enum mlx5_pci_status {
645 MLX5_PCI_STATUS_DISABLED,
646 MLX5_PCI_STATUS_ENABLED,
647};
648
649enum mlx5_pagefault_type_flags {
650 MLX5_PFAULT_REQUESTOR = 1 << 0,
651 MLX5_PFAULT_WRITE = 1 << 1,
652 MLX5_PFAULT_RDMA = 1 << 2,
653};
654
655struct mlx5_td {
656 /* protects tirs list changes while tirs refresh */
657 struct mutex list_lock;
658 struct list_head tirs_list;
659 u32 tdn;
660};
661
662struct mlx5e_resources {
663 struct mlx5e_hw_objs {
664 u32 pdn;
665 struct mlx5_td td;
666 u32 mkey;
667 struct mlx5_sq_bfreg *bfregs;
668 unsigned int num_bfregs;
669#define MLX5_MAX_NUM_TC 8
670 u32 tisn[MLX5_MAX_PORTS][MLX5_MAX_NUM_TC];
671 bool tisn_valid;
672 } hw_objs;
673 struct net_device *uplink_netdev;
674 netdevice_tracker tracker;
675 struct mutex uplink_netdev_lock;
676 struct mlx5_crypto_dek_priv *dek_priv;
677};
678
679enum mlx5_sw_icm_type {
680 MLX5_SW_ICM_TYPE_STEERING,
681 MLX5_SW_ICM_TYPE_HEADER_MODIFY,
682 MLX5_SW_ICM_TYPE_HEADER_MODIFY_PATTERN,
683 MLX5_SW_ICM_TYPE_SW_ENCAP,
684};
685
686#define MLX5_MAX_RESERVED_GIDS 8
687
688struct mlx5_rsvd_gids {
689 unsigned int start;
690 unsigned int count;
691 struct ida ida;
692};
693
694struct mlx5_clock;
695struct mlx5_clock_dev_state;
696struct mlx5_dm;
697struct mlx5_fw_tracer;
698struct mlx5_vxlan;
699struct mlx5_geneve;
700struct mlx5_hv_vhca;
701struct mlx5_st;
702
703#define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
704#define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
705
706enum {
707 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
708 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
709};
710
711enum {
712 MKEY_CACHE_LAST_STD_ENTRY = 20,
713 MLX5_IMR_KSM_CACHE_ENTRY,
714 MAX_MKEY_CACHE_ENTRIES
715};
716
717struct mlx5_profile {
718 u64 mask;
719 u8 log_max_qp;
720 u8 num_cmd_caches;
721 struct {
722 int size;
723 int limit;
724 } mr_cache[MAX_MKEY_CACHE_ENTRIES];
725};
726
727struct mlx5_hca_cap {
728 u32 cur[MLX5_UN_SZ_DW(hca_cap_union)];
729 u32 max[MLX5_UN_SZ_DW(hca_cap_union)];
730};
731
732enum mlx5_wc_state {
733 MLX5_WC_STATE_UNINITIALIZED,
734 MLX5_WC_STATE_UNSUPPORTED,
735 MLX5_WC_STATE_SUPPORTED,
736};
737
738struct mlx5_core_dev {
739 struct device *device;
740 enum mlx5_coredev_type coredev_type;
741 struct pci_dev *pdev;
742 /* sync pci state */
743 struct mutex pci_status_mutex;
744 enum mlx5_pci_status pci_status;
745 u8 rev_id;
746 char board_id[MLX5_BOARD_ID_LEN];
747 struct mlx5_cmd cmd;
748 struct {
749 struct mlx5_hca_cap *hca[MLX5_CAP_NUM];
750 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
751 u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
752 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
753 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
754 u8 embedded_cpu;
755 } caps;
756 struct mlx5_timeouts *timeouts;
757 u64 sys_image_guid;
758 phys_addr_t iseg_base;
759 struct mlx5_init_seg __iomem *iseg;
760 phys_addr_t bar_addr;
761 enum mlx5_device_state state;
762 /* sync interface state */
763 struct mutex intf_state_mutex;
764 struct lock_class_key lock_key;
765 unsigned long intf_state;
766 struct mlx5_priv priv;
767 struct mlx5_profile profile;
768 u32 issi;
769 struct mlx5e_resources mlx5e_res;
770 struct mlx5_dm *dm;
771 struct mlx5_st *st;
772 struct mlx5_vxlan *vxlan;
773 struct mlx5_geneve *geneve;
774 struct {
775 struct mlx5_rsvd_gids reserved_gids;
776 u32 roce_en;
777 } roce;
778#ifdef CONFIG_MLX5_FPGA
779 struct mlx5_fpga_device *fpga;
780#endif
781 struct mlx5_clock *clock;
782 struct mlx5_clock_dev_state *clock_state;
783 struct mlx5_ib_clock_info *clock_info;
784 struct mlx5_fw_tracer *tracer;
785 struct mlx5_rsc_dump *rsc_dump;
786 u32 vsc_addr;
787 struct mlx5_hv_vhca *hv_vhca;
788 struct mlx5_hwmon *hwmon;
789 u64 num_block_tc;
790 u64 num_block_ipsec;
791#ifdef CONFIG_MLX5_MACSEC
792 struct mlx5_macsec_fs *macsec_fs;
793 /* MACsec notifier chain to sync MACsec core and IB database */
794 struct blocking_notifier_head macsec_nh;
795#endif
796 u64 num_ipsec_offloads;
797 struct mlx5_sd *sd;
798 enum mlx5_wc_state wc_state;
799 /* sync write combining state */
800 struct mutex wc_state_lock;
801};
802
803struct mlx5_db {
804 __be32 *db;
805 union {
806 struct mlx5_db_pgdir *pgdir;
807 struct mlx5_ib_user_db_page *user_page;
808 } u;
809 dma_addr_t dma;
810 int index;
811};
812
813#define MLX5_DEFAULT_NUM_DOORBELLS 8
814
815enum {
816 MLX5_COMP_EQ_SIZE = 1024,
817};
818
819enum {
820 MLX5_PTYS_IB = 1 << 0,
821 MLX5_PTYS_EN = 1 << 2,
822};
823
824typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
825
826enum {
827 MLX5_CMD_ENT_STATE_PENDING_COMP,
828 MLX5_CMD_ENT_STATE_TIMEDOUT,
829};
830
831struct mlx5_cmd_work_ent {
832 unsigned long state;
833 struct mlx5_cmd_msg *in;
834 struct mlx5_cmd_msg *out;
835 void *uout;
836 int uout_size;
837 mlx5_cmd_cbk_t callback;
838 struct delayed_work cb_timeout_work;
839 void *context;
840 int idx;
841 struct completion handling;
842 struct completion slotted;
843 struct completion done;
844 struct mlx5_cmd *cmd;
845 struct work_struct work;
846 struct mlx5_cmd_layout *lay;
847 int ret;
848 int page_queue;
849 u8 status;
850 u8 token;
851 u64 ts1;
852 u64 ts2;
853 u16 op;
854 bool polling;
855 /* Track the max comp handlers */
856 refcount_t refcnt;
857};
858
859enum phy_port_state {
860 MLX5_AAA_111
861};
862
863struct mlx5_hca_vport_context {
864 u32 field_select;
865 bool sm_virt_aware;
866 bool has_smi;
867 bool has_raw;
868 enum port_state_policy policy;
869 enum phy_port_state phys_state;
870 enum ib_port_state vport_state;
871 u8 port_physical_state;
872 u64 sys_image_guid;
873 u64 port_guid;
874 u64 node_guid;
875 u32 cap_mask1;
876 u32 cap_mask1_perm;
877 u16 cap_mask2;
878 u16 cap_mask2_perm;
879 u16 lid;
880 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
881 u8 lmc;
882 u8 subnet_timeout;
883 u16 sm_lid;
884 u8 sm_sl;
885 u16 qkey_violation_counter;
886 u16 pkey_violation_counter;
887 bool grh_required;
888 u8 num_plane;
889};
890
891#define STRUCT_FIELD(header, field) \
892 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
893 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
894
895extern struct dentry *mlx5_debugfs_root;
896
897static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
898{
899 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
900}
901
902static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
903{
904 return ioread32be(&dev->iseg->fw_rev) >> 16;
905}
906
907static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
908{
909 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
910}
911
912static inline u32 mlx5_base_mkey(const u32 key)
913{
914 return key & 0xffffff00u;
915}
916
917static inline u32 wq_get_byte_sz(u8 log_sz, u8 log_stride)
918{
919 return ((u32)1 << log_sz) << log_stride;
920}
921
922static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
923 u8 log_stride, u8 log_sz,
924 u16 strides_offset,
925 struct mlx5_frag_buf_ctrl *fbc)
926{
927 fbc->frags = frags;
928 fbc->log_stride = log_stride;
929 fbc->log_sz = log_sz;
930 fbc->sz_m1 = (1 << fbc->log_sz) - 1;
931 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
932 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1;
933 fbc->strides_offset = strides_offset;
934}
935
936static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
937 u8 log_stride, u8 log_sz,
938 struct mlx5_frag_buf_ctrl *fbc)
939{
940 mlx5_init_fbc_offset(frags, log_stride, log_sz, strides_offset: 0, fbc);
941}
942
943static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
944 u32 ix)
945{
946 unsigned int frag;
947
948 ix += fbc->strides_offset;
949 frag = ix >> fbc->log_frag_strides;
950
951 return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
952}
953
954static inline u32
955mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
956{
957 u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
958
959 return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
960}
961
962enum {
963 CMD_ALLOWED_OPCODE_ALL,
964};
965
966void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
967void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
968void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
969
970struct mlx5_async_ctx {
971 struct mlx5_core_dev *dev;
972 atomic_t num_inflight;
973 struct completion inflight_done;
974};
975
976struct mlx5_async_work;
977
978typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
979
980struct mlx5_async_work {
981 struct mlx5_async_ctx *ctx;
982 mlx5_async_cbk_t user_callback;
983 u16 opcode; /* cmd opcode */
984 u16 op_mod; /* cmd op_mod */
985 u8 throttle_locked:1;
986 u8 unpriv_locked:1;
987 void *out; /* pointer to the cmd output buffer */
988};
989
990void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
991 struct mlx5_async_ctx *ctx);
992void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
993int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
994 void *out, int out_size, mlx5_async_cbk_t callback,
995 struct mlx5_async_work *work);
996void mlx5_cmd_out_err(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out);
997int mlx5_cmd_do(struct mlx5_core_dev *dev, void *in, int in_size, void *out, int out_size);
998int mlx5_cmd_check(struct mlx5_core_dev *dev, int err, void *in, void *out);
999int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1000 int out_size);
1001
1002#define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out) \
1003 ({ \
1004 mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out, \
1005 MLX5_ST_SZ_BYTES(ifc_cmd##_out)); \
1006 })
1007
1008#define mlx5_cmd_exec_in(dev, ifc_cmd, in) \
1009 ({ \
1010 u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {}; \
1011 mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out); \
1012 })
1013
1014int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1015 void *out, int out_size);
1016bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
1017int mlx5_cmd_add_privileged_uid(struct mlx5_core_dev *dev, u16 uid);
1018void mlx5_cmd_remove_privileged_uid(struct mlx5_core_dev *dev, u16 uid);
1019
1020void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *mdev, struct net_device *netdev);
1021void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *mdev);
1022
1023void mlx5_core_mp_event_replay(struct mlx5_core_dev *dev, u32 event, void *data);
1024
1025void mlx5_health_cleanup(struct mlx5_core_dev *dev);
1026int mlx5_health_init(struct mlx5_core_dev *dev);
1027void mlx5_start_health_poll(struct mlx5_core_dev *dev);
1028void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
1029void mlx5_start_health_fw_log_up(struct mlx5_core_dev *dev);
1030void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1031void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1032int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1033 struct mlx5_frag_buf *buf, int node);
1034void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1035int mlx5_core_create_mkey(struct mlx5_core_dev *dev, u32 *mkey, u32 *in,
1036 int inlen);
1037int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, u32 mkey);
1038int mlx5_core_query_mkey(struct mlx5_core_dev *dev, u32 mkey, u32 *out,
1039 int outlen);
1040int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1041int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1042int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1043void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1044void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1045void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1046void mlx5_pages_debugfs_init(struct mlx5_core_dev *dev);
1047void mlx5_pages_debugfs_cleanup(struct mlx5_core_dev *dev);
1048int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1049int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1050void mlx5_register_debugfs(void);
1051void mlx5_unregister_debugfs(void);
1052
1053void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
1054void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1055int mlx5_comp_eqn_get(struct mlx5_core_dev *dev, u16 vecidx, int *eqn);
1056int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1057int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1058
1059struct dentry *mlx5_debugfs_get_dev_root(struct mlx5_core_dev *dev);
1060void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1061void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1062int mlx5_access_reg(struct mlx5_core_dev *dev, void *data_in, int size_in,
1063 void *data_out, int size_out, u16 reg_id, int arg,
1064 int write, bool verbose);
1065int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1066 int size_in, void *data_out, int size_out,
1067 u16 reg_num, int arg, int write);
1068
1069int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1070 int node);
1071
1072static inline int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db)
1073{
1074 return mlx5_db_alloc_node(dev, db, node: dev->priv.numa_node);
1075}
1076
1077void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1078
1079const char *mlx5_command_str(int command);
1080void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1081void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1082int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1083 int npsvs, u32 *sig_index);
1084int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1085__be32 mlx5_core_get_terminate_scatter_list_mkey(struct mlx5_core_dev *dev);
1086void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1087
1088int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1089void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1090int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1091 struct mlx5_rate_limit *rl);
1092void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1093bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1094int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1095 bool dedicated_entry, u16 *index);
1096void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1097bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1098 struct mlx5_rate_limit *rl_1);
1099int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1100 bool map_wc, bool fast_path);
1101void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1102
1103unsigned int mlx5_comp_vectors_max(struct mlx5_core_dev *dev);
1104int mlx5_comp_vector_get_cpu(struct mlx5_core_dev *dev, int vector);
1105unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1106int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1107 u8 roce_version, u8 roce_l3_type, const u8 *gid,
1108 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1109
1110static inline u32 mlx5_mkey_to_idx(u32 mkey)
1111{
1112 return mkey >> 8;
1113}
1114
1115static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1116{
1117 return mkey_idx << 8;
1118}
1119
1120static inline u8 mlx5_mkey_variant(u32 mkey)
1121{
1122 return mkey & 0xff;
1123}
1124
1125/* Async-atomic event notifier used by mlx5 core to forward FW
1126 * evetns received from event queue to mlx5 consumers.
1127 * Optimise event queue dipatching.
1128 */
1129int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1130int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1131
1132/* Async-atomic event notifier used for forwarding
1133 * evetns from the event queue into the to mlx5 events dispatcher,
1134 * eswitch, clock and others.
1135 */
1136int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1137int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1138
1139/* Blocking event notifier used to forward SW events, used for slow path */
1140int mlx5_blocking_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1141int mlx5_blocking_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1142int mlx5_blocking_notifier_call_chain(struct mlx5_core_dev *dev, unsigned int event,
1143 void *data);
1144
1145int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1146
1147int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1148int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1149bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1150bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1151bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1152bool mlx5_lag_mode_is_hash(struct mlx5_core_dev *dev);
1153bool mlx5_lag_is_master(struct mlx5_core_dev *dev);
1154bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev);
1155bool mlx5_lag_is_mpesw(struct mlx5_core_dev *dev);
1156u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
1157 struct net_device *slave);
1158int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1159 u64 *values,
1160 int num_counters,
1161 size_t *offsets);
1162struct mlx5_core_dev *mlx5_lag_get_next_peer_mdev(struct mlx5_core_dev *dev, int *i);
1163
1164#define mlx5_lag_for_each_peer_mdev(dev, peer, i) \
1165 for (i = 0, peer = mlx5_lag_get_next_peer_mdev(dev, &i); \
1166 peer; \
1167 peer = mlx5_lag_get_next_peer_mdev(dev, &i))
1168
1169u8 mlx5_lag_get_num_ports(struct mlx5_core_dev *dev);
1170struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1171void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1172int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1173 u64 length, u32 log_alignment, u16 uid,
1174 phys_addr_t *addr, u32 *obj_id);
1175int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1176 u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1177
1178#ifdef CONFIG_PCIE_TPH
1179int mlx5_st_alloc_index(struct mlx5_core_dev *dev, enum tph_mem_type mem_type,
1180 unsigned int cpu_uid, u16 *st_index);
1181int mlx5_st_dealloc_index(struct mlx5_core_dev *dev, u16 st_index);
1182#else
1183static inline int mlx5_st_alloc_index(struct mlx5_core_dev *dev,
1184 enum tph_mem_type mem_type,
1185 unsigned int cpu_uid, u16 *st_index)
1186{
1187 return -EOPNOTSUPP;
1188}
1189static inline int mlx5_st_dealloc_index(struct mlx5_core_dev *dev, u16 st_index)
1190{
1191 return -EOPNOTSUPP;
1192}
1193#endif
1194
1195struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev);
1196void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev);
1197
1198int mlx5_sriov_blocking_notifier_register(struct mlx5_core_dev *mdev,
1199 int vf_id,
1200 struct notifier_block *nb);
1201void mlx5_sriov_blocking_notifier_unregister(struct mlx5_core_dev *mdev,
1202 int vf_id,
1203 struct notifier_block *nb);
1204int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1205 struct ib_device *device,
1206 struct rdma_netdev_alloc_params *params);
1207
1208enum {
1209 MLX5_PCI_DEV_IS_VF = 1 << 0,
1210};
1211
1212static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1213{
1214 return dev->coredev_type == MLX5_COREDEV_PF;
1215}
1216
1217static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1218{
1219 return dev->coredev_type == MLX5_COREDEV_VF;
1220}
1221
1222static inline bool mlx5_core_same_coredev_type(const struct mlx5_core_dev *dev1,
1223 const struct mlx5_core_dev *dev2)
1224{
1225 return dev1->coredev_type == dev2->coredev_type;
1226}
1227
1228static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
1229{
1230 return dev->caps.embedded_cpu;
1231}
1232
1233static inline bool
1234mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1235{
1236 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1237}
1238
1239static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1240{
1241 return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1242}
1243
1244static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1245{
1246 return dev->priv.sriov.max_vfs;
1247}
1248
1249static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev *dev)
1250{
1251 /* LACP owner conditions:
1252 * 1) Function is physical.
1253 * 2) LAG is supported by FW.
1254 * 3) LAG is managed by driver (currently the only option).
1255 */
1256 return MLX5_CAP_GEN(dev, vport_group_manager) &&
1257 (MLX5_CAP_GEN(dev, num_lag_ports) > 1) &&
1258 MLX5_CAP_GEN(dev, lag_master);
1259}
1260
1261static inline u16 mlx5_core_max_ec_vfs(const struct mlx5_core_dev *dev)
1262{
1263 return dev->priv.sriov.max_ec_vfs;
1264}
1265
1266static inline int mlx5_get_gid_table_len(u16 param)
1267{
1268 if (param > 4) {
1269 pr_warn("gid table length is zero\n");
1270 return 0;
1271 }
1272
1273 return 8 * (1 << param);
1274}
1275
1276static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1277{
1278 return !!(dev->priv.rl_table.max_size);
1279}
1280
1281static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1282{
1283 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1284 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1285}
1286
1287static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1288{
1289 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1290}
1291
1292static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1293{
1294 return mlx5_core_is_mp_slave(dev) ||
1295 mlx5_core_is_mp_master(dev);
1296}
1297
1298static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1299{
1300 if (!mlx5_core_mp_enabled(dev))
1301 return 1;
1302
1303 return MLX5_CAP_GEN(dev, native_port_num);
1304}
1305
1306static inline int mlx5_get_dev_index(struct mlx5_core_dev *dev)
1307{
1308 int idx = MLX5_CAP_GEN(dev, native_port_num);
1309
1310 if (idx >= 1 && idx <= MLX5_MAX_PORTS)
1311 return idx - 1;
1312 else
1313 return PCI_FUNC(dev->pdev->devfn);
1314}
1315
1316enum {
1317 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1318};
1319
1320bool mlx5_is_roce_on(struct mlx5_core_dev *dev);
1321
1322static inline bool mlx5_get_roce_state(struct mlx5_core_dev *dev)
1323{
1324 if (MLX5_CAP_GEN(dev, roce_rw_supported))
1325 return MLX5_CAP_GEN(dev, roce);
1326
1327 /* If RoCE cap is read-only in FW, get RoCE state from devlink
1328 * in order to support RoCE enable/disable feature
1329 */
1330 return mlx5_is_roce_on(dev);
1331}
1332
1333#ifdef CONFIG_MLX5_MACSEC
1334static inline bool mlx5e_is_macsec_device(const struct mlx5_core_dev *mdev)
1335{
1336 if (!(MLX5_CAP_GEN_64(mdev, general_obj_types) &
1337 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD))
1338 return false;
1339
1340 if (!MLX5_CAP_GEN(mdev, log_max_dek))
1341 return false;
1342
1343 if (!MLX5_CAP_MACSEC(mdev, log_max_macsec_offload))
1344 return false;
1345
1346 if (!MLX5_CAP_FLOWTABLE_NIC_RX(mdev, macsec_decrypt) ||
1347 !MLX5_CAP_FLOWTABLE_NIC_RX(mdev, reformat_remove_macsec))
1348 return false;
1349
1350 if (!MLX5_CAP_FLOWTABLE_NIC_TX(mdev, macsec_encrypt) ||
1351 !MLX5_CAP_FLOWTABLE_NIC_TX(mdev, reformat_add_macsec))
1352 return false;
1353
1354 if (!MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_128_encrypt) &&
1355 !MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_256_encrypt))
1356 return false;
1357
1358 if (!MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_128_decrypt) &&
1359 !MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_256_decrypt))
1360 return false;
1361
1362 return true;
1363}
1364
1365#define NIC_RDMA_BOTH_DIRS_CAPS (MLX5_FT_NIC_RX_2_NIC_RX_RDMA | MLX5_FT_NIC_TX_RDMA_2_NIC_TX)
1366
1367static inline bool mlx5_is_macsec_roce_supported(struct mlx5_core_dev *mdev)
1368{
1369 if (((MLX5_CAP_GEN_2(mdev, flow_table_type_2_type) &
1370 NIC_RDMA_BOTH_DIRS_CAPS) != NIC_RDMA_BOTH_DIRS_CAPS) ||
1371 !MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, max_modify_header_actions) ||
1372 !mlx5e_is_macsec_device(mdev) || !mdev->macsec_fs)
1373 return false;
1374
1375 return true;
1376}
1377#endif
1378
1379enum {
1380 MLX5_OCTWORD = 16,
1381};
1382
1383bool mlx5_wc_support_get(struct mlx5_core_dev *mdev);
1384
1385static inline struct net *mlx5_core_net(struct mlx5_core_dev *dev)
1386{
1387 return devlink_net(devlink: priv_to_devlink(priv: dev));
1388}
1389
1390#define MLX5_SW_IMAGE_GUID_MAX_BYTES 9
1391
1392#endif /* MLX5_DRIVER_H */
1393

source code of linux/include/linux/mlx5/driver.h

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