1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * linux/include/asm-arm/hardware/serial_amba.h
4 *
5 * Internal header file for AMBA serial ports
6 *
7 * Copyright (C) ARM Limited
8 * Copyright (C) 2000 Deep Blue Solutions Ltd.
9 */
10#ifndef ASM_ARM_HARDWARE_SERIAL_AMBA_H
11#define ASM_ARM_HARDWARE_SERIAL_AMBA_H
12
13#ifndef __ASSEMBLY__
14#include <linux/bitfield.h>
15#include <linux/bits.h>
16#endif
17
18#include <linux/types.h>
19
20/* -------------------------------------------------------------------------------
21 * From AMBA UART (PL010) Block Specification
22 * -------------------------------------------------------------------------------
23 * UART Register Offsets.
24 */
25#define UART01x_DR 0x00 /* Data read or written from the interface. */
26#define UART01x_RSR 0x04 /* Receive status register (Read). */
27#define UART01x_ECR 0x04 /* Error clear register (Write). */
28#define UART010_LCRH 0x08 /* Line control register, high byte. */
29#define ST_UART011_DMAWM 0x08 /* DMA watermark configure register. */
30#define UART010_LCRM 0x0C /* Line control register, middle byte. */
31#define ST_UART011_TIMEOUT 0x0C /* Timeout period register. */
32#define UART010_LCRL 0x10 /* Line control register, low byte. */
33#define UART010_CR 0x14 /* Control register. */
34#define UART01x_FR 0x18 /* Flag register (Read only). */
35#define UART010_IIR 0x1C /* Interrupt identification register (Read). */
36#define UART010_ICR 0x1C /* Interrupt clear register (Write). */
37#define ST_UART011_LCRH_RX 0x1C /* Rx line control register. */
38#define UART01x_ILPR 0x20 /* IrDA low power counter register. */
39#define UART011_IBRD 0x24 /* Integer baud rate divisor register. */
40#define UART011_FBRD 0x28 /* Fractional baud rate divisor register. */
41#define UART011_LCRH 0x2c /* Line control register. */
42#define ST_UART011_LCRH_TX 0x2c /* Tx Line control register. */
43#define UART011_CR 0x30 /* Control register. */
44#define UART011_IFLS 0x34 /* Interrupt fifo level select. */
45#define UART011_IMSC 0x38 /* Interrupt mask. */
46#define UART011_RIS 0x3c /* Raw interrupt status. */
47#define UART011_MIS 0x40 /* Masked interrupt status. */
48#define UART011_ICR 0x44 /* Interrupt clear register. */
49#define UART011_DMACR 0x48 /* DMA control register. */
50#define ST_UART011_XFCR 0x50 /* XON/XOFF control register. */
51#define ST_UART011_XON1 0x54 /* XON1 register. */
52#define ST_UART011_XON2 0x58 /* XON2 register. */
53#define ST_UART011_XOFF1 0x5C /* XON1 register. */
54#define ST_UART011_XOFF2 0x60 /* XON2 register. */
55#define ST_UART011_ITCR 0x80 /* Integration test control register. */
56#define ST_UART011_ITIP 0x84 /* Integration test input register. */
57#define ST_UART011_ABCR 0x100 /* Autobaud control register. */
58#define ST_UART011_ABIMSC 0x15C /* Autobaud interrupt mask/clear register. */
59
60/*
61 * ZTE UART register offsets. This UART has a radically different address
62 * allocation from the ARM and ST variants, so we list all registers here.
63 * We assume unlisted registers do not exist.
64 */
65#define ZX_UART011_DR 0x04
66#define ZX_UART011_FR 0x14
67#define ZX_UART011_IBRD 0x24
68#define ZX_UART011_FBRD 0x28
69#define ZX_UART011_LCRH 0x30
70#define ZX_UART011_CR 0x34
71#define ZX_UART011_IFLS 0x38
72#define ZX_UART011_IMSC 0x40
73#define ZX_UART011_RIS 0x44
74#define ZX_UART011_MIS 0x48
75#define ZX_UART011_ICR 0x4c
76#define ZX_UART011_DMACR 0x50
77
78#define UART011_DR_OE BIT(11)
79#define UART011_DR_BE BIT(10)
80#define UART011_DR_PE BIT(9)
81#define UART011_DR_FE BIT(8)
82
83#define UART01x_RSR_OE BIT(3)
84#define UART01x_RSR_BE BIT(2)
85#define UART01x_RSR_PE BIT(1)
86#define UART01x_RSR_FE BIT(0)
87
88#define UART011_FR_RI BIT(8)
89#define UART011_FR_TXFE BIT(7)
90#define UART011_FR_RXFF BIT(6)
91#define UART01x_FR_TXFF (1 << 5) /* used in ASM */
92#define UART01x_FR_RXFE BIT(4)
93#define UART01x_FR_BUSY (1 << 3) /* used in ASM */
94#define UART01x_FR_DCD BIT(2)
95#define UART01x_FR_DSR BIT(1)
96#define UART01x_FR_CTS BIT(0)
97#define UART01x_FR_TMSK (UART01x_FR_TXFF + UART01x_FR_BUSY)
98
99/*
100 * Some bits of Flag Register on ZTE device have different position from
101 * standard ones.
102 */
103#define ZX_UART01x_FR_BUSY BIT(8)
104#define ZX_UART01x_FR_DSR BIT(3)
105#define ZX_UART01x_FR_CTS BIT(1)
106#define ZX_UART011_FR_RI BIT(0)
107
108#define UART011_CR_CTSEN BIT(15) /* CTS hardware flow control */
109#define UART011_CR_RTSEN BIT(14) /* RTS hardware flow control */
110#define UART011_CR_OUT2 BIT(13) /* OUT2 */
111#define UART011_CR_OUT1 BIT(12) /* OUT1 */
112#define UART011_CR_RTS BIT(11) /* RTS */
113#define UART011_CR_DTR BIT(10) /* DTR */
114#define UART011_CR_RXE BIT(9) /* receive enable */
115#define UART011_CR_TXE BIT(8) /* transmit enable */
116#define UART011_CR_LBE BIT(7) /* loopback enable */
117#define UART010_CR_RTIE BIT(6)
118#define UART010_CR_TIE BIT(5)
119#define UART010_CR_RIE BIT(4)
120#define UART010_CR_MSIE BIT(3)
121#define ST_UART011_CR_OVSFACT BIT(3) /* Oversampling factor */
122#define UART01x_CR_IIRLP BIT(2) /* SIR low power mode */
123#define UART01x_CR_SIREN BIT(1) /* SIR enable */
124#define UART01x_CR_UARTEN BIT(0) /* UART enable */
125
126#define UART011_LCRH_SPS BIT(7)
127#define UART01x_LCRH_WLEN_8 0x60
128#define UART01x_LCRH_WLEN_7 0x40
129#define UART01x_LCRH_WLEN_6 0x20
130#define UART01x_LCRH_WLEN_5 0x00
131#define UART01x_LCRH_FEN BIT(4)
132#define UART01x_LCRH_STP2 BIT(3)
133#define UART01x_LCRH_EPS BIT(2)
134#define UART01x_LCRH_PEN BIT(1)
135#define UART01x_LCRH_BRK BIT(0)
136
137#define ST_UART011_DMAWM_RX GENMASK(5, 3)
138#define ST_UART011_DMAWM_RX_1 FIELD_PREP_CONST(ST_UART011_DMAWM_RX, 0)
139#define ST_UART011_DMAWM_RX_2 FIELD_PREP_CONST(ST_UART011_DMAWM_RX, 1)
140#define ST_UART011_DMAWM_RX_4 FIELD_PREP_CONST(ST_UART011_DMAWM_RX, 2)
141#define ST_UART011_DMAWM_RX_8 FIELD_PREP_CONST(ST_UART011_DMAWM_RX, 3)
142#define ST_UART011_DMAWM_RX_16 FIELD_PREP_CONST(ST_UART011_DMAWM_RX, 4)
143#define ST_UART011_DMAWM_RX_32 FIELD_PREP_CONST(ST_UART011_DMAWM_RX, 5)
144#define ST_UART011_DMAWM_RX_48 FIELD_PREP_CONST(ST_UART011_DMAWM_RX, 6)
145#define ST_UART011_DMAWM_TX GENMASK(2, 0)
146#define ST_UART011_DMAWM_TX_1 FIELD_PREP_CONST(ST_UART011_DMAWM_TX, 0)
147#define ST_UART011_DMAWM_TX_2 FIELD_PREP_CONST(ST_UART011_DMAWM_TX, 1)
148#define ST_UART011_DMAWM_TX_4 FIELD_PREP_CONST(ST_UART011_DMAWM_TX, 2)
149#define ST_UART011_DMAWM_TX_8 FIELD_PREP_CONST(ST_UART011_DMAWM_TX, 3)
150#define ST_UART011_DMAWM_TX_16 FIELD_PREP_CONST(ST_UART011_DMAWM_TX, 4)
151#define ST_UART011_DMAWM_TX_32 FIELD_PREP_CONST(ST_UART011_DMAWM_TX, 5)
152#define ST_UART011_DMAWM_TX_48 FIELD_PREP_CONST(ST_UART011_DMAWM_TX, 6)
153
154#define UART010_IIR_RTIS BIT(3)
155#define UART010_IIR_TIS BIT(2)
156#define UART010_IIR_RIS BIT(1)
157#define UART010_IIR_MIS BIT(0)
158
159#define UART011_IFLS_RXIFLSEL GENMASK(5, 3)
160#define UART011_IFLS_RX1_8 FIELD_PREP_CONST(UART011_IFLS_RXIFLSEL, 0)
161#define UART011_IFLS_RX2_8 FIELD_PREP_CONST(UART011_IFLS_RXIFLSEL, 1)
162#define UART011_IFLS_RX4_8 FIELD_PREP_CONST(UART011_IFLS_RXIFLSEL, 2)
163#define UART011_IFLS_RX6_8 FIELD_PREP_CONST(UART011_IFLS_RXIFLSEL, 3)
164#define UART011_IFLS_RX7_8 FIELD_PREP_CONST(UART011_IFLS_RXIFLSEL, 4)
165#define UART011_IFLS_TXIFLSEL GENMASK(2, 0)
166#define UART011_IFLS_TX1_8 FIELD_PREP_CONST(UART011_IFLS_TXIFLSEL, 0)
167#define UART011_IFLS_TX2_8 FIELD_PREP_CONST(UART011_IFLS_TXIFLSEL, 1)
168#define UART011_IFLS_TX4_8 FIELD_PREP_CONST(UART011_IFLS_TXIFLSEL, 2)
169#define UART011_IFLS_TX6_8 FIELD_PREP_CONST(UART011_IFLS_TXIFLSEL, 3)
170#define UART011_IFLS_TX7_8 FIELD_PREP_CONST(UART011_IFLS_TXIFLSEL, 4)
171/* special values for ST vendor with deeper fifo */
172#define UART011_IFLS_RX_HALF FIELD_PREP_CONST(UART011_IFLS_RXIFLSEL, 5)
173#define UART011_IFLS_TX_HALF FIELD_PREP_CONST(UART011_IFLS_TXIFLSEL, 5)
174
175#define UART011_OEIM BIT(10) /* overrun error interrupt mask */
176#define UART011_BEIM BIT(9) /* break error interrupt mask */
177#define UART011_PEIM BIT(8) /* parity error interrupt mask */
178#define UART011_FEIM BIT(7) /* framing error interrupt mask */
179#define UART011_RTIM BIT(6) /* receive timeout interrupt mask */
180#define UART011_TXIM BIT(5) /* transmit interrupt mask */
181#define UART011_RXIM BIT(4) /* receive interrupt mask */
182#define UART011_DSRMIM BIT(3) /* DSR interrupt mask */
183#define UART011_DCDMIM BIT(2) /* DCD interrupt mask */
184#define UART011_CTSMIM BIT(1) /* CTS interrupt mask */
185#define UART011_RIMIM BIT(0) /* RI interrupt mask */
186
187#define UART011_OEIS BIT(10) /* overrun error interrupt status */
188#define UART011_BEIS BIT(9) /* break error interrupt status */
189#define UART011_PEIS BIT(8) /* parity error interrupt status */
190#define UART011_FEIS BIT(7) /* framing error interrupt status */
191#define UART011_RTIS BIT(6) /* receive timeout interrupt status */
192#define UART011_TXIS BIT(5) /* transmit interrupt status */
193#define UART011_RXIS BIT(4) /* receive interrupt status */
194#define UART011_DSRMIS BIT(3) /* DSR interrupt status */
195#define UART011_DCDMIS BIT(2) /* DCD interrupt status */
196#define UART011_CTSMIS BIT(1) /* CTS interrupt status */
197#define UART011_RIMIS BIT(0) /* RI interrupt status */
198
199#define UART011_OEIC BIT(10) /* overrun error interrupt clear */
200#define UART011_BEIC BIT(9) /* break error interrupt clear */
201#define UART011_PEIC BIT(8) /* parity error interrupt clear */
202#define UART011_FEIC BIT(7) /* framing error interrupt clear */
203#define UART011_RTIC BIT(6) /* receive timeout interrupt clear */
204#define UART011_TXIC BIT(5) /* transmit interrupt clear */
205#define UART011_RXIC BIT(4) /* receive interrupt clear */
206#define UART011_DSRMIC BIT(3) /* DSR interrupt clear */
207#define UART011_DCDMIC BIT(2) /* DCD interrupt clear */
208#define UART011_CTSMIC BIT(1) /* CTS interrupt clear */
209#define UART011_RIMIC BIT(0) /* RI interrupt clear */
210
211#define UART011_DMAONERR BIT(2) /* disable dma on error */
212#define UART011_TXDMAE BIT(1) /* enable transmit dma */
213#define UART011_RXDMAE BIT(0) /* enable receive dma */
214
215#define UART01x_RSR_ANY (UART01x_RSR_OE | UART01x_RSR_BE | UART01x_RSR_PE | UART01x_RSR_FE)
216#define UART01x_FR_MODEM_ANY (UART01x_FR_DCD | UART01x_FR_DSR | UART01x_FR_CTS)
217
218#ifndef __ASSEMBLY__
219struct amba_device; /* in uncompress this is included but amba/bus.h is not */
220struct amba_pl010_data {
221 void (*set_mctrl)(struct amba_device *dev, void __iomem *base, unsigned int mctrl);
222};
223
224struct dma_chan;
225struct amba_pl011_data {
226 bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
227 void *dma_rx_param;
228 void *dma_tx_param;
229 bool dma_rx_poll_enable;
230 unsigned int dma_rx_poll_rate;
231 unsigned int dma_rx_poll_timeout;
232 void (*init)(void);
233 void (*exit)(void);
234};
235#endif
236
237#endif
238

source code of linux/include/linux/amba/serial.h

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